ATmega88PA Automotive Atmel Corporation, ATmega88PA Automotive Datasheet - Page 246

• Manufacturer Part Number: ATmega88PA Automotive
• Manufacturer: Atmel Corporation

246
Atmel ATmega48PA/88PA/168PA [Preliminary]
• Bit 6 – ACBG: Analog Comparator Bandgap Select
When this bit is set, a fixed bandgap reference voltage replaces the positive input to the Ana-
log Comparator. When this bit is cleared, AIN0 is applied to the positive input of the Analog
Comparator. When the bandgap reference is used as input to the Analog Comparator, it will
take a certain time for the voltage to stabilize. If not stabilized, the first conversion may give a
wrong value. See
• Bit 5 – ACO: Analog Comparator Output
The output of the Analog Comparator is synchronized and then directly connected to ACO.
The synchronization introduces a delay of 1 - 2 clock cycles.
• Bit 4 – ACI: Analog Comparator Interrupt Flag
This bit is set by hardware when a comparator output event triggers the interrupt mode defined
by ACIS1 and ACIS0. The Analog Comparator interrupt routine is executed if the ACIE bit is
set and the I-bit in SREG is set. ACI is cleared by hardware when executing the corresponding
interrupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag.
• Bit 3 – ACIE: Analog Comparator Interrupt Enable
When the ACIE bit is written logic one and the I-bit in the Status Register is set, the Analog
Comparator interrupt is activated. When written logic zero, the interrupt is disabled.
• Bit 2 – ACIC: Analog Comparator Input Capture Enable
When written logic one, this bit enables the input capture function in Timer/Counter1 to be trig-
gered by the Analog Comparator. The comparator output is in this case directly connected to
the input capture front-end logic, making the comparator utilize the noise canceler and edge
select features of the Timer/Counter1 Input Capture interrupt. When written logic zero, no con-
nection between the Analog Comparator and the input capture function exists. To make the
comparator trigger the Timer/Counter1 Input Capture interrupt, the ICIE1 bit in the Timer Inter-
rupt Mask Register (TIMSK1) must be set.
• Bits 1, 0 – ACIS1, ACIS0: Analog Comparator Interrupt Mode Select
These bits determine which comparator events that trigger the Analog Comparator interrupt.
The different settings are shown in
Table 23-2.
When changing the ACIS1/ACIS0 bits, the Analog Comparator Interrupt must be disabled by
clearing its Interrupt Enable bit in the ACSR Register. Otherwise an interrupt can occur when
the bits are changed.
ACIS1
0
0
1
1
ACIS1/ACIS0 Settings
ACIS0
“Internal Voltage Reference” on page 51
0
1
0
1
Interrupt Mode
Comparator Interrupt on Output Toggle.
Reserved
Comparator Interrupt on Falling Output Edge.
Comparator Interrupt on Rising Output Edge.
Table
23-2.
9223B–AVR–09/11