ATmega88PA Automotive Atmel Corporation, ATmega88PA Automotive Datasheet - Page 137

• Manufacturer Part Number: ATmega88PA Automotive
• Manufacturer: Atmel Corporation

16.11.4
16.11.5
16.11.6
9223B–AVR–09/11
TCNT1H and TCNT1L – Timer/Counter1
OCR1AH and OCR1AL – Output Compare Register 1 A
OCR1BH and OCR1BL – Output Compare Register 1 B
The two Timer/Counter I/O locations (TCNT1H and TCNT1L, combined TCNT1) give direct
access, both for read and for write operations, to the Timer/Counter unit 16-bit counter. To
ensure that both the high and low bytes are read and written simultaneously when the CPU
accesses these registers, the access is performed using an 8-bit temporary High Byte Regis-
ter (TEMP). This temporary register is shared by all the other 16-bit registers.
16-bit Registers” on page 113.
Modifying the counter (TCNT1) while the counter is running introduces a risk of missing a
compare match between TCNT1 and one of the OCR1x Registers.
Writing to the TCNT1 Register blocks (removes) the compare match on the following timer
clock for all compare units.
The Output Compare Registers contain a 16-bit value that is continuously compared with the
counter value (TCNT1). A match can be used to generate an Output Compare interrupt, or to
generate a waveform output on the OC1x pin.
The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes
are written simultaneously when the CPU writes to these registers, the access is performed
using an 8-bit temporary High Byte Register (TEMP). This temporary register is shared by all
the other 16-bit registers.
Bit
(0x85)
(0x84)
Read/Write
Initial Value
Bit
(0x89)
(0x88)
Read/Write
Initial Value
Bit
(0x8B)
(0x8A)
Read/Write
Initial Value
Atmel ATmega48PA/88PA/168PA [Preliminary]
R/W
R/W
R/W
7
0
7
0
7
0
R/W
R/W
R/W
See “Accessing 16-bit Registers” on page 113.
6
0
6
0
6
0
R/W
R/W
R/W
5
0
5
0
5
0
R/W
R/W
R/W
4
OCR1A[15:8]
0
4
OCR1B[15:8]
0
4
0
TCNT1[15:8]
OCR1A[7:0]
OCR1B[7:0]
TCNT1[7:0]
R/W
R/W
R/W
3
0
3
0
3
0
R/W
R/W
R/W
2
0
2
0
2
0
R/W
R/W
R/W
1
0
1
0
1
0
R/W
R/W
R/W
See “Accessing
0
0
0
0
0
0
OCR1AH
OCR1AL
OCR1BH
OCR1BL
TCNT1H
TCNT1L
137