ATmega88PA Automotive Atmel Corporation, ATmega88PA Automotive Datasheet - Page 74

• Manufacturer Part Number: ATmega88PA Automotive
• Manufacturer: Atmel Corporation

14.2
14.2.1
74
Ports as General Digital I/O
Atmel ATmega48PA/88PA/168PA [Preliminary]
Configuring the Pin
The ports are bi-directional I/O ports with optional internal pull-ups.
tional description of one I/O-port pin, here generically called Pxn.
Figure 14-2. General Digital I/O
Note:
Each port pin consists of three register bits: DDxn, PORTxn, and PINxn. As shown in
ter Description” on page
PORTxn bits at the PORTx I/O address, and the PINxn bits at the PINx I/O address.
The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written logic one,
Pxn is configured as an output pin. If DDxn is written logic zero, Pxn is configured as an input
pin.
If PORTxn is written logic one when the pin is configured as an input pin, the pull-up resistor is
activated. To switch the pull-up resistor off, PORTxn has to be written logic zero or the pin has
to be configured as an output pin. The port pins are tri-stated when reset condition becomes
active, even if no clocks are running.
If PORTxn is written logic one when the pin is configured as an output pin, the port pin is
driven high (one). If PORTxn is written logic zero when the pin is configured as an output pin,
the port pin is driven low (zero).
Pxn
1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk
SLEEP, and PUD are common to all ports.
PUD:
SLEEP:
clk
I/O
:
PULLUP DISABLE
SLEEP CONTROL
I/O CLOCK
91, the DDxn bits are accessed at the DDRx I/O address, the
(1)
SLEEP
SYNCHRONIZER
WDx:
RDx:
WRx:
RRx:
RPx:
WPx:
D
L
Q
Q
D
PINxn
WRITE DDRx
READ DDRx
WRITE PORTx
READ PORTx REGISTER
READ PORTx PIN
WRITE PINx REGISTER
Q
Q
RESET
RESET
PORTxn
Q
Q
Q
Q
DDxn
CLR
CLR
D
D
Figure 14-2
RRx
PUD
WDx
RDx
RPx
clk
1
0
WRx
I/O
shows a func-
9223B–AVR–09/11
WPx
“Regis-
I/O
,