ATmega88PA Automotive Atmel Corporation, ATmega88PA Automotive Datasheet - Page 177

• Manufacturer Part Number: ATmega88PA Automotive
• Manufacturer: Atmel Corporation

20.3
9223B–AVR–09/11
Clock Generation
Figure 20-1. USART Block Diagram
Note:
The Clock Generation logic generates the base clock for the Transmitter and Receiver. The
USART supports four modes of clock operation: Normal asynchronous, Double Speed asyn-
chronous, Master synchronous and Slave synchronous mode. The UMSELn bit in USART
Control and Status Register C (UCSRnC) selects between asynchronous and synchronous
operation. Double Speed (asynchronous mode only) is controlled by the U2Xn found in the
UCSRnA Register. When using synchronous mode (UMSELn = 1), the Data Direction Regis-
ter for the XCKn pin (DDR_XCKn) controls whether the clock source is internal (Master mode)
or external (Slave mode). The XCKn pin is only active when using synchronous mode.
Atmel ATmega48PA/88PA/168PA [Preliminary]
1. Refer to
Figure 1-1 on page 2
UCSRnA
TRANSMIT SHIFT REGISTER
RECEIVE SHIFT REGISTER
BAUD RATE GENERATOR
UDRn (Receive)
UDRn(Transmit)
UBRRn [H:L]
(1)
and
Table 14-9 on page 88
UCSRnB
GENERATOR
SYNC LOGIC
RECOVERY
RECOVERY
CHECKER
PARITY
PARITY
CLOCK
DATA
OSC
for USART0 pin placement.
Clock Generator
CONTROL
CONTROL
CONTROL
CONTROL
CONTROL
Transmitter
PIN
PIN
PIN
TX
RX
Receiver
UCSRnC
XCKn
TxDn
RxDn
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