ATmega88PA Automotive Atmel Corporation, ATmega88PA Automotive Datasheet - Page 252

• Manufacturer Part Number: ATmega88PA Automotive
• Manufacturer: Atmel Corporation

Figure 24-4. ADC Timing Diagram, First Conversion (Single Conversion Mode)
Figure 24-5. ADC Timing Diagram, Single Conversion
252
Cycle Number
ADC Clock
ADEN
ADSC
ADIF
ADCH
ADCL
Cycle Number
ADC Clock
ADSC
ADIF
ADCH
ADCL
Atmel ATmega48PA/88PA/168PA [Preliminary]
1
2
1
MUX and REFS
Update
The actual sample-and-hold takes place 1.5 ADC clock cycles after the start of a normal con-
version and 13.5 ADC clock cycles after the start of an first conversion. When a conversion is
complete, the result is written to the ADC Data Registers, and ADIF is set. In Single Conver-
sion mode, ADSC is cleared simultaneously. The software may then set ADSC again, and a
new conversion will be initiated on the first rising ADC clock edge.
When Auto Triggering is used, the prescaler is reset when the trigger event occurs. This
assures a fixed delay from the trigger event to the start of conversion. In this mode, the sam-
ple-and-hold takes place two ADC clock cycles after the rising edge on the trigger source
signal. Three additional CPU clock cycles are used for synchronization logic.
In Free Running mode, a new conversion will be started immediately after the conversion
completes, while ADSC remains high. For a summary of conversion times, see
page
2
MUX and REFS
Update
253.
12
3
13
Sample & Hold
4
14
5
15
Sample & Hold
6
16
First Conversion
17
7
One Conversion
18
8
19
9
20
10
Conversion
Complete
21
11
22
Conversion
Complete
12
23
13
24
25
Sign and MSB of Result
LSB of Result
Sign and MSB of Result
Next Conversion
1
Next
Conversion
1
LSB of Result
2
MUX and REFS
Update
2
MUX and REFS
Update
3
Table 24-1 on
9223B–AVR–09/11
3