AD9789 Analog Devices, AD9789 Datasheet - Page 27

• Manufacturer Part Number: AD9789
• Description: 14-Bit, 2400 MSPS RF DAC with 4-Channel Signal Processing
• Manufacturer: Analog Devices

Specifications of AD9789

• Resolution (bits): 14bit
• Dac Update Rate: 2.4GSPS
• Dac Settling Time: 13ns
• Max Pos Supply (v): +3.47V
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: LVDS,Par

SPI REGISTER MAP
Do not write to the following registers unless instructed otherwise: Register 0x34, Register 0x35, Register 0x37, Register 0x3B, Register 0x3F,
or Register 0x40 through Register 0x55.
Table 11. Register Map
Addr
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
Register Name
SPI control
Saturation
counter
Parity counter
Interrupt enable
Interrupt
status/clear
Channel enable
Bypass
QAM/SRRC
configuration
Summing node
scalar
Input scalar
NCO 0 frequency
tuning word
NCO 1 frequency
tuning word
NCO 2 frequency
tuning word
NCO 3 frequency
tuning word
Rate converter
denominator (Q)
Rate converter
numerator (P)
Interpolating BPF
center frequency
Frequency update
Hardware version
Interface
configuration
Data control
DCO frequency
Internal clock
phase adjust
Parameter update
Channel 0 gain
Channel 1 gain
Channel 2 gain
Channel 3 gain
Spectrum shaping
SDIO_DIR
PARERR
QAM
BIN
Reserved
PARMNEW
Bit 7
PARERR
CMOS_BUS
FREQNEW
Reserved
Bit 6
LSBFIRST
BISTDONE
BISTDONE
SRRC
CMOS_CTRL
BUSWDTH[1:0]
DSCPHZ[3:0]
Reserved
Reserved
DCODIV[2:0]
Bit 5
RESET
PARMSET
PARMSET
Reserved
Reserved
Rev. A | Page 27 of 76
ALPHA[1:0]
Reserved
Bit 4
LNG_INST
PARMCLR
PARMCLR
DCO_INV
DATWDTH
CHAN0GAIN[7:0]
CHAN1GAIN[7:0]
CHAN2GAIN[7:0]
CHAN3GAIN[7:0]
SUMSCALE[7:0]
INSCALE[7:0]
SATCNT[7:0]
PARCNT[7:0]
FTW0[23:16]
FTW1[23:16]
FTW2[23:16]
FTW3[23:16]
FTW0[15:8]
FTW1[15:8]
FTW2[15:8]
FTW3[15:8]
FTW0[7:0]
FTW1[7:0]
FTW2[7:0]
FTW3[7:0]
Q[23:16]
P[23:16]
FC[15:8]
Q[15:8]
FC[7:0]
P[15:8]
Q[7:0]
P[7:0]
Reserved
Reserved
Bit 3
LOCKACQ
LOCKACQ
Reserved
IF_MODE
CMPLX
INT[4:0]
Bit 2
LOCKLOST
LOCKLOST
CHANPRI
CHANEN[3:0]
SNCPHZ[3:0]
ONES[3:0]
VER[3:0]
MAPPING[2:0]
LTNCY[2:0]
Bit 1
SATERR
SATERR
PAR[1:0]
Bit 0
Reserved
Reserved
SPEC_INV
AD9789
De-
fault
0x18
0x00
0x00
0x00
0x00
0x00
0x00
0x01
0x0D
0x20
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x80
0x00
0x00
0x80
0x00
0x00
0x00
0x03
0xC8
0x61
0x1F
0x85
0x00
0x80
0x80
0x80
0x80
0x00