AD9789 Analog Devices, AD9789 Datasheet - Page 68

• Manufacturer Part Number: AD9789
• Description: 14-Bit, 2400 MSPS RF DAC with 4-Channel Signal Processing
• Manufacturer: Analog Devices

Specifications of AD9789

• Resolution (bits): 14bit
• Dac Update Rate: 2.4GSPS
• Dac Settling Time: 13ns
• Max Pos Supply (v): +3.47V
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: LVDS,Par

AD9789
CHANNELIZER MODE PIN MAPPING FOR CMOS AND LVDS
Table 93 lists the available combinations of data input configu-
ration parameters when the AD9789 is in channelizer mode.
Many of these configurations require multiple clocks to load all
channels. All of these configurations are described in detail in
Table 96 and Table 97.
Table 94 and Table 95, along with Figure 128 and Figure 129,
describe CMOS and LVDS data input pin mapping. CMOS
mode is always single data rate and samples on the rising edge
of DSC. LVDS mode is single data rate (SDR) for bus widths
of 4 bits through 16 bits and double data rate (DDR) for a bus
width of 32 bits.
Table 93. Data Input Configurations for Channelizer Mode
Bus Width
4
4
8
8
8
16
16
16
32
32
32
Table 94. CMOS Pin Assignments for Various Interface Widths
Interface Width
4 bits
8 bits
16 bits
32 bits
Table 95. LVDS Pin Assignments for Various Interface Widths
Interface Width
4 bits
8 bits
16 bits
32 bits
Data Width
8
8
8
8
16
8
8
16
8
8
16
Pin Assignments
D[3:0]
D[7:0]
D[15:0]
D[31:0]
Pin Assignments
D[3:0]P, D[3:0]N
D[7:0]P, D[7:0]N
D[15:0]P, D[15:0]N
D[15:0]P, D[15:0]N rising
edge and falling edge
Data Format
Real
Complex
Real
Complex
Complex
Real
Complex
Complex
Real
Complex
Complex
BUSWDTH[1:0]
00
01
10
11
BUSWDTH[1:0]
00
01
10
11
Rev. A | Page 68 of 76
PARN
PARP
G
M
A
B
C
D
E
H
K
N
P
F
J
L
1
M
B
C
D
G
H
K
N
A
E
F
P
J
L
2
1
3
2
Figure 128. CMOS Data Input Pin Mapping
P1
P0
Figure 129. LVDS Data Input Pin Mapping
4
3
D[31:0] CMOS DATA INPUTS
PARITY AND CONTROL INPUTS
31 27 23 19 15 11
30 26 22 18 14 10
29 25 21 17 13
28 24 20 16 12
5
P+
P–
4
6
14
15 13 11
15 13 11
14 12 10
14 12 10
5
+LVDS
7
6
8
7
9
14 –LVDS
8
9
9
8
8
10
9
8
6
6
9
7
7
11
4
7
6
5
10
5
5
4
4
12
1
0
3
2
11
3
3
2
2
13
12
1
1
0
0
1
BU
CT
DC
FS
4
13
DC
DC
FS
FS
CMOS_BUS
CMOS_CTRL
CMOS_FS
CMOS_DCO
1
4
FSP
FSN
DCOP
DCON