AD9789 Analog Devices, AD9789 Datasheet - Page 31

• Manufacturer Part Number: AD9789
• Description: 14-Bit, 2400 MSPS RF DAC with 4-Channel Signal Processing
• Manufacturer: Analog Devices

Specifications of AD9789

• Resolution (bits): 14bit
• Dac Update Rate: 2.4GSPS
• Dac Settling Time: 13ns
• Max Pos Supply (v): +3.47V
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: LVDS,Par

Table 19. QAM/SRRC Configuration Register (Address 0x07)
Bit
[7:6]
[5:4]
3
[2:0]
Table 20. Summing Node Scalar Register (Address 0x08)
Bit
[7:0]
Table 21. Input Scalar Register (Address 0x09)
Bit
[7:0]
Bit Name
Reserved
ALPHA[1:0]
Reserved
MAPPING[2:0]
Bit Name
SUMSCALE[7:0]
Bit Name
INSCALE[7:0]
Description
This register sets the value of the 2.6 multiplier that is applied to the output of the channel summing node.
Setting
00000000
00000001
00000010
…
00001101
…
11111110
11111111
Description
This register sets the value of the 3.5 multiplier that is applied to the input data. This scaling block is in parallel
with the QAM encoder block and is used when the QAM encoder block is bypassed.
Setting
00000000
00000001
00000010
…
00100000
…
11111110
11111111
Description
Reserved.
These bits set the SRRC filter alpha.
Setting
00
01
10
11
Reserved.
These bits set the QAM encoding.
Setting
000
001
010
011
100
101
110
111
Alpha Filter
0.12
0.18
0.15
0.13
QAM Encoding
DOCSIS 64-QAM
DOCSIS 256-QAM
DVB-C 16-QAM
DVB-C 32-QAM
DVB-C 64-QAM
DVB-C 128-QAM
DVB-C 256-QAM
Unused
2.6 Multiplier
0
0.015625
0.03125
…
0.203125 (default)
…
3.96875
3.984375
3.5 Multiplier
0
0.03125
0.0625
…
1 (default)
…
7.9375
7.96875
Rev. A | Page 31 of 76
AD9789