AD9789 Analog Devices, AD9789 Datasheet - Page 54

• Manufacturer Part Number: AD9789
• Description: 14-Bit, 2400 MSPS RF DAC with 4-Channel Signal Processing
• Manufacturer: Analog Devices

Specifications of AD9789

• Resolution (bits): 14bit
• Dac Update Rate: 2.4GSPS
• Dac Settling Time: 13ns
• Max Pos Supply (v): +3.47V
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: LVDS,Par

AD9789
In QDUC mode, where the interface is fixed at a 32-bit bus
width, the parity behavior is straightforward (see Table 73).
Table 73. Parity Behavior in QDUC Mode
Inter-
face
CMOS
LVDS
(DDR)
1
In channelizer mode, where the interface is configurable for
different bus widths, data widths, and data formats, the parity
bits check the data-word on the bus.
For example, consider a configuration in channelizer mode where
the bus width is 4, the data width is 8, and the data format is
real. In this case, eight clock cycles are required to transfer all of
the baud rate data to represent four channels. In the even parity
or odd parity mode, one parity bit and four data bits are sent on
each clock; the parity bit checks the four data bits to verify that
all of the data was sent over the interface.
Table 74 summarizes the behavior of the two parity pins and
how they interact with the data in all interface modes.
Table 74. Parity Behavior in Channelizer Mode
Inter-
face
CMOS
CMOS
CMOS
CMOS
LVDS
(SDR)
LVDS
(SDR)
LVDS
(SDR)
LVDS
(DDR)
1
“Rising” corresponds to the data sampled on the rising edge of DSC; “falling”
“Rising” corresponds to the data sampled on the rising edge of DSC; “falling”
corresponds to the data sampled on the falling edge of DSC.
corresponds to the data sampled on the falling edge of DSC.
1
1
1
1
1
Bus
Width
4 bits
8 bits
16 bits
32 bits
4 bits
8 bits
16 bits
32 bits
Bus
Width
32 bits
32 bits
Even/Odd Parity
P1 ignored
P0 checks D[3:0]
P1 ignored
P0 checks D[7:0]
P1 ignored
P0 checks D[15:0]
P1 checks D[31:16]
P0 checks D[15:0]
[PARP, PARN] falling checks
D[3:0]P, D[3:0]N falling
[PARP, PARN] falling checks
D[7:0]P, D[7:0]N falling
[PARP, PARN] falling checks
D[15:0]P, D[15:0]N falling
[PARP, PARN] rising checks
D[15:0]P, D[15:0]N rising
[PARP, PARN] falling checks
D[15:0]P, D[15:0]N falling
Even/Odd Parity
P1 checks D[31:16]
P0 checks D[15:0]
[PARP, PARN] rising checks
D[15:0]P, D[15:0]N rising
[PARP, PARN] falling checks
D[15:0]P, D[15:0]N falling
IQ Parity
P1 = 0
P0 = 1
P1 = 0
P0 = 1
P1 = 0
P0 = 1
P1 = 0
P0 = 1
Not supported
Not supported
Not supported
PARP rising = 0
PARN rising = 1
PARP falling = 1
PARN falling = 0
IQ Parity
P1 = 0
P0 = 1
PARP rising = 0
PARN rising = 1
PARP falling = 1
PARN falling = 0
Rev. A | Page 54 of 76
If a parity error occurs, the parity counter (Register 0x02[7:0])
is incremented. The parity counter continues to accumulate
until it is cleared or until it reaches a maximum value of 255.
The count can be cleared by writing a 1 to Register 0x04[7].
An IRQ can be enabled to trigger when a parity error occurs by
writing a 1 to Register 0x03[7]. The status of IRQ can be meas-
ured via Register 0x04[7] or by using the IRQ pin (Pin P2). If
using the IRQ pin and more than one IRQ is enabled, the user
must check Register 0x04 when an IRQ event occurs to determine
whether the IRQ was caused by a parity error. The IRQ can also
be cleared by writing a 1 to Register 0x04[7].
ANALOG MODES OF OPERATION
The AD9789 uses a quad-switch architecture that can be config-
ured to operate in one of three modes via the serial peripheral
interface: normal mode, RZ mode, and mix mode.
The quad-switch architecture masks the code-dependent glitches
that occur in a conventional two-switch DAC. Figure 104 shows
the waveforms for a conventional DAC and the quad-switch DAC.
In the two-switch architecture with D1 and D2 in different states,
a switch transition results in a glitch. However, if D1 and D2 are
at the same state, the switch does not create a glitch. This code-
dependent glitching causes an increased amount of distortion in
the DAC. In the quad-switch architecture, two switches are
always transitioning at each half clock cycle, regardless of the
code; therefore, code-dependent glitches are eliminated, but a
constant glitch at 2 × f
(NORMAL MODE)
The quad-switch architecture can also be easily configured to
perform an analog mix or return-to-zero (RZ) function. In mix
mode, the output is effectively chopped at the DAC sample rate.
The RZ mode is similar to mix mode, except that the inter-
mediate data samples are replaced with midscale values instead
of inverting values. Figure 105 shows the DAC waveforms for
both mix mode and RZ mode.
DAC OUTPUT
DAC OUTPUT
INPUT DATA
2-SWITCH
4-SWITCH
DACCLK
Figure 104. Two-Switch and Quad-Switch DAC Waveforms
D1
D1
D1
D2
D2
D2
DAC
D3
is created.
D3
D3
D4
D4
D4
D5
D5
D5
D6
D6
D6
D7
D7
D7
D8
D8
D8
D9
D9
D9
D10
D10
D10
t
t