AD9789 Analog Devices, AD9789 Datasheet - Page 33

• Manufacturer Part Number: AD9789
• Description: 14-Bit, 2400 MSPS RF DAC with 4-Channel Signal Processing
• Manufacturer: Analog Devices

Specifications of AD9789

• Resolution (bits): 14bit
• Dac Update Rate: 2.4GSPS
• Dac Settling Time: 13ns
• Max Pos Supply (v): +3.47V
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: LVDS,Par

The two interpolating BPF center frequency registers together compose the 16-bit center frequency of the 16× band-pass interpolation
filter. For more information about programming these registers, see the Digital 16× Tunable Band-Pass Filter section.
Table 28. Interpolating BPF Center Frequency Registers (Address 0x1C and Address 0x1D)
Address
0x1C
0x1D
Table 29. Frequency Update Register (Address 0x1E)
Bit
7
[6:0]
Table 30. Hardware Version Register (Address 0x1F)
Bit
[7:4]
[3:0]
Table 31. Interface Configuration Register (Address 0x20)
Bit
7
6
5
4
3
2
[1:0]
Name
FREQNEW
Reserved
Name
Reserved
VER[3:0]
Bit Name
CMOS_BUS
CMOS_CTRL
Reserved
DCO_INV
IF_MODE
CHANPRI
PAR[1:0]
Bit Name
FC[7:0]
FC[15:8]
Description
Setting this bit to 1 updates the derived registers in the AD9789. This bit must be set for changes to Register 0x16
through Register 0x1D to take effect. This self-clearing bit is reset to 0 after the derived registers are updated.
Reserved.
Description
Reserved.
This read-only register indicates the version of the chip (0011).
Description
This bit reflects the state of the CMOS_BUS pin (L14).
This bit reflects the state of the CMOS_CTRL pin (M14).
Reserved.
When set to 1, the DCO pin is inverted.
This bit sets the data interface mode.
0 = channelizer mode. Supports all available interface widths and 8- and 16-bit word widths. Supports maximum
f
1 = quadrature digital upconverter (QDUC) mode. Supports 32-bit interface, 16-bit word mode only. Supports
maximum f
This bit selects the channel prioritization value (used in channelizer mode only).
0 = device expects input samples only for those channels that are enabled.
1 = device expects data for all four channels. Data for disabled channels is expected and must be sent, but this
data is discarded by the AD9789.
These bits set the parity checking. For more information, see the Parity section.
Setting
00
01
10
11
BAUD
of f
DAC
/48.
BAUD
Description
Center frequency, Bits[7:0]
Center frequency, Bits[15:8]
of f
DAC
/16.
Even parity
Parity Checking
Parity checking deactivated
IQ parity (a value of 0 is expected on the I channel and a value of 1 is expected on the
Q channel)
Odd parity
Rev. A | Page 33 of 76
AD9789