AD9789 Analog Devices, AD9789 Datasheet - Page 39

• Manufacturer Part Number: AD9789
• Description: 14-Bit, 2400 MSPS RF DAC with 4-Channel Signal Processing
• Manufacturer: Analog Devices

Specifications of AD9789

• Resolution (bits): 14bit
• Dac Update Rate: 2.4GSPS
• Dac Settling Time: 13ns
• Max Pos Supply (v): +3.47V
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: LVDS,Par

THEORY OF OPERATION
The AD9789 is a flexible digital signal processing (DSP) engine
combined with a high performance, 2400 MSPS, 14-bit DAC
(Figure 70). The DSP blocks include a QAM encoder, a 2×
upsampling square root raised cosine (SRRC) filter, selectable
interpolation from 16× to 512×, a rate converter, and a complex
modulator. The digital interface can accept up to four channels
of complex data. The QAM encoder supports constellation sizes
of 16, 32, 64, 128, and 256. The on-chip rate converter allows
fine resolution of baud rates with a fixed DAC sampling clock.
The digital upconverters can place the input signals from dc to
0.5 × f
into the second and third DAC Nyquist zones.
Control of the AD9789 functions is via a serial peripheral
interface (SPI).
DATAPATH SIGNAL PROCESSING
The DSP blocks included on the AD9789 can be grouped into
two sections. The first is the datapath signal processing. Four
identical datapaths, or channels, can be used. A block diagram
of a single channel is shown in Figure 71. Enabling and disabling
each DSP block within the datapath takes effect on all channels.
There is independent control of the scaling and the frequency
placement of each channel.
The following sections describe each of the DSP blocks
included in the datapath.
32 INPUT
2 PARITY
PINS
PINS
AND
DCO
INSCALE
FS
MAPPER
QAM
DAC
. An analog mix mode extends the output spectrum
BYPASS
16 TO 31
0 TO 15
CMOS
CMOS
QAM
LVDS
RISE
LVDS
FALL
Figure 70. Top Level Functional Block Diagram
Figure 71. Datapath Block Diagram
SRRC
2
DATA
DATA
DATA
DATA
BYPASS
FILTER/
FILTER/
FILTER/
FILTER/
SRRC
QAM/
QAM/
QAM/
QAM/
NCO
NCO
NCO
NCO
(N = 0 TO 5)
2
N
INTERPOLATOR
+ SCALARS
AND BPF
CONVERTER
(P/Q = 0.5 TO 1)
SPI
P/Q 24-BIT
16×
RATE
IRQ RS
0 TO
24-BIT NCO
2.4GSPS
f
DAC
14-BIT
CH GAIN
0× TO 2×
DAC
/16
Rev. A | Page 39 of 76
QAM Encoder
The QAM encoder supports seven different standards-compliant
mappings. (For illustrations of the supported mappings, see the
QAM Constellation Maps section.) The QAM encoder receives
input data-words of 8 bits in width and maps them into 16, 32,
64, 128, or 256 point constellations. It outputs 5-bit complex
QAM modulated samples. The mode in which the QAM
encoder runs is selected via the QAM/SRRC configuration
register (Register 0x07[2:0]).
Table 50 lists the available QAM mapper modes along with the
corresponding input bits and output range. The operation of the
QAM encoder when configured in DOCSIS 64-QAM mode is
described in this section. The operation of the QAM encoder in
the other modes is conceptually the same; only the input data
bit encoding and scale factors are different.
The DOCSIS 64-QAM constellation diagram is shown in
Figure
encoder input is mapped into the QAM constellation. For
example, an input data-word of 111111 maps to the constellation
point in the upper right corner of the 64-QAM constellation.
110,100 111,000 010,100 011,000 100,000 101,010 110,000 111,010
110,111 111,011 010,111 011,011 100,101 101,111 110,101 111,111
100,111 101,011 000,111 001,011 000,101 001,111 010,101 011,111
100,100 101,000 000,100 001,000 000,000 001,010 010,000 011,010
010,011 011,001 000,011 001,001 000,001 001,101 100,001 101,101
010,110 011,100 000,110 001,100 000,010 001,110 100,010 101,110
110,011 111,001 100,011 101,001 010,001 011,101 110,001 111,101
110,110 111,100 100,110 101,100 010,010 011,110 110,010 111,110
73
. The constellation diagram shows how the QAM
FROM INPUT
INTERFACE
Figure 73. DOCSIS 64-QAM Constellation
Figure 72. QAM Encoder I/O
8
Q
ENCODER
QAM
C5 C4 C3, C2 C1 C0
5
5
I
Q
AD9789
I