AD9789 Analog Devices, AD9789 Datasheet - Page 63

• Manufacturer Part Number: AD9789
• Description: 14-Bit, 2400 MSPS RF DAC with 4-Channel Signal Processing
• Manufacturer: Analog Devices

Specifications of AD9789

• Resolution (bits): 14bit
• Dac Update Rate: 2.4GSPS
• Dac Settling Time: 13ns
• Max Pos Supply (v): +3.47V
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: LVDS,Par

CUSTOMER BIST MODES
USING THE INTERNAL PRN GENERATOR TO TEST
QAM OUTPUT AC PERFORMANCE
The AD9789 can be configured to enable an on-chip pseudo-
random number (PRN) generator. The PRN output is connected
to the front end of the datapath and disconnects the datapath
from the input pins. In this way, the PRN generator can be used
in conjunction with the on-chip QAM encoder to generate a
QAM output. The PRN generator allows the user to measure
the ac performance of a QAM signal at the DAC output without
an external data source. To enable the internal PRN generator
via the serial port, follow these steps.
1.
Table 80. Register Settings to Configure the Clock
Register
0x30
0x31
0x32
2.
Table 81. Register Settings to Configure PRN Generation
Register
0x42
0x43
0x44
0x45
0x46
0x47
0x49
0x4B
0x4C
0x4D
0x05
3.
4.
Table 82. Register Settings to Start PRN Generation
Register
0x48
0x4A
0x40
Ensure that the clock is enabled and that the clock
common-mode level is set to its optimal value by setting
the registers in Table 80 to the values shown in the table.
Configure BIST mode for PRN generation and disconnect
the inputs by setting the registers in Table 81 to the values
shown in the table.
Cycle the PARMNEW bit to ensure that the digital clocks
are active by first setting Register 0x24 to 0x00, and then
setting Register 0x24 to 0x80.
Start PRN generation by setting the registers in Table 82 to
the values shown in the table.
Data
0x80
0xF0
0x9E
Description
Enable duty cycle correction.
Set the common-mode level of CLKN:
CLKN_CML = 0xF.
Set the common-mode level of CLKP:
CLKP_CML = 0xF. Set PSIGN = 0, NSIGN = 0.
Enable clock receiver (CLK_DIS = 1).
Setting
0x10
0x00
0x10
0x00
0x00
0x10
0x16
0x17
0x4E
0x1F
0x0F
Setting
0xAB
0xAB
0x56
Rev. A | Page 63 of 76
After the PRN generator is started, users can freely configure
the datapath for their desired test configuration as long as
Register 0x40 to Register 0x55 are not modified.
To disable the PRN generator, write 0x00 to Register 0x40.
USING THE INTERNAL BUILT-IN SELF-TEST (BIST)
TO TEST FOR DIGITAL DATA INPUT CONNECTIVITY
The AD9789 includes an internal built-in self-test (BIST) engine
that processes incoming data and creates a signature that can be
read back via the serial port. This BIST feature can be configured
to observe the static state of the digital data input pins (L4 to
L12, M4 to M12, N5 to N12, and P5 to P12) and to reflect the
state of these pins via the signature registers (Register 0x50 to
Register 0x55). In this way, the user can verify digital data input
connectivity.
Testing Connectivity for LVDS Interface Mode
To test the connectivity of the digital data input pins in LVDS
interface mode, follow these steps.
1.
Table 83. Register Settings to Configure the Clock
Register
0x30
0x31
0x32
2.
3.
Table 84. Register Settings for LVDS Interface
Register
0x20
0x21
0x22
0x23
Ensure that the clock is enabled and that the clock
common-mode level is set to its optimal value by setting
the registers in Table 83 to the values shown in the table.
Cycle the PARMNEW bit to ensure that the digital clocks
are active by first setting Register 0x24 to 0x00, and then
setting Register 0x24 to 0x80.
Configure the LVDS interface for high speed, 16-bit bus
width, 16-bit data width operation by setting the registers
in Table 84 to the values shown in the table.
Data
0x80
0xF0
0x9E
Description
Enable duty cycle correction.
Set the common-mode level of CLKN:
CLKN_CML = 0xF.
Set the common-mode level of CLKP:
CLKP_CML = 0xF. Set PSIGN = 0, NSIGN = 0.
Enable clock receiver (CLK_DIS = 1).
Setting
0x08
0x41
0x1F
0x87
AD9789