AD9789 Analog Devices, AD9789 Datasheet - Page 64

• Manufacturer Part Number: AD9789
• Description: 14-Bit, 2400 MSPS RF DAC with 4-Channel Signal Processing
• Manufacturer: Analog Devices

Specifications of AD9789

• Resolution (bits): 14bit
• Dac Update Rate: 2.4GSPS
• Dac Settling Time: 13ns
• Max Pos Supply (v): +3.47V
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: LVDS,Par

AD9789
4.
Table 85. Register Settings to Configure Pin Modes
Register
0x42
0x43
0x44
0x45
0x46
0x47
0x49
0x4B
0x4C
0x4D
5.
6.
7.
Table 86. Register Settings for BIST Pin Test
Register
0x48
0x4A
0x40
8.
Table 87. Signature Register Settings
Register
0x50
0x51
0x52
0x53
0x54
0x55
Testing Connectivity for CMOS Interface Mode
To test the connectivity of the digital data input pins in CMOS
interface mode, follow these steps.
1.
Table 88. Register Settings to Configure the Clock
Register
0x30
0x31
0x32
Configure pin mode by setting the registers in Table 85 to
the values shown in the table.
Cycle the PARMNEW bit to ensure that the interface
configuration was updated by first setting Register 0x24
to 0x00, and then setting Register 0x24 to 0x80.
Apply static LVDS data to the input ports.
Enable the BIST pin test by setting the registers in Table 86
to the values shown in the table.
Read back the signature registers (Register 0x50 to
Register 0x55) to determine the pin states (see Table 87).
Ensure that the clock is enabled and that the clock
common-mode level is set to its optimal value by setting
the registers in Table 88 to the values shown in the table.
Data
0xF0
0x9E
0x80
Setting
0x00
0x08
0x00
0x08
0x00
0x10
0x1C
0x1C
0x00
0x00
Setting
0x80
0x80
0x55
Associated LVDS Pairs
Data bits D[7:0]
Data bits D[15:8]
Parity PAR
Data bits D[7:0] (repeated)
Data bits D[15:8] (repeated)
Parity PAR (repeated)
Description
Enable duty cycle correction.
Set the common-mode level of CLKN:
CLKN_CML = 0xF.
Set the common-mode level of CLKP:
CLKP_CML = 0xF. Set PSIGN = 0, NSIGN = 0.
Enable clock receiver (CLK_DIS = 1).
Rev. A | Page 64 of 76
2.
3.
Table 89. Register Settings for CMOS Interface
Register
0x20
0x21
0x22
0x23
4.
Table 90. Register Settings to Configure Pin Modes
Register
0x42
0x43
0x44
0x45
0x46
0x47
0x49
0x4B
0x4C
0x4D
5.
6.
7.
Table 91. Register Settings for BIST Pin Test
Register
0x48
0x4A
0x40
8.
Table 92. Signature Register Settings
Register
0x50
0x51
0x52
0x53
0x54
0x55
Cycle the PARMNEW bit to ensure that the digital clocks
are active by first setting Register 0x24 to 0x00, and then
setting Register 0x24 to 0x80.
Configure the CMOS interface for high speed, 32-bit bus
width, 16-bit data width operation by setting the registers
in Table 89 to the values shown in the table.
Configure pin mode by setting the registers in Table 90 to
the values shown in the table.
Cycle the PARMNEW bit to ensure that the interface
configuration was updated by first setting Register 0x24
to 0x00, and then setting Register 0x24 to 0x80.
Apply static CMOS data to the input ports.
Enable the BIST pin test by setting the registers in Table 91
to the values shown in the table.
Read back the signature registers (Register 0x50 to Register
0x55) to determine the pin states (see Table 92).
Setting
0x08
0x61
0x1F
0x87
Setting
0x00
0x08
0x00
0x08
0x00
0x10
0x1C
0x1C
0x00
0x00
Setting
0x80
0x80
0x55
Associated CMOS Pairs
Data bits D[23:16]
Data bits D[31:24]
Parity P1
Data bits D[7:0]
Data bits [D15:8]
Parity P0