AD9789 Analog Devices, AD9789 Datasheet - Page 5

• Manufacturer Part Number: AD9789
• Description: 14-Bit, 2400 MSPS RF DAC with 4-Channel Signal Processing
• Manufacturer: Analog Devices

Specifications of AD9789

• Resolution (bits): 14bit
• Dac Update Rate: 2.4GSPS
• Dac Settling Time: 13ns
• Max Pos Supply (v): +3.47V
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: LVDS,Par

DIGITAL SPECIFICATIONS
AVDD33 = DVDD33 = 3.3 V, CVDD18 = DVDD18 = 1.8 V, DVDD15 = 1.5 V, f
are compliant with the IEEE Std 1596.3-1996 reduced range link, unless otherwise noted.
Table 2.
Parameter
CMOS DATA INPUTS (D[31:0], P0, P1)
CMOS OUTPUTS (CMOS_FS, CMOS_DCO)
LVDS DATA INPUTS (D[15:0]P, D[15:0]N, PARP, PARN)
LVDS OUTPUTS (DCOP, DCON, FSP, FSN)
DAC CLOCK INPUT (CLKP, CLKN)
SERIAL PERIPHERAL INTERFACE
Input Voltage High, V
Input Voltage Low, V
Input Current High, I
Input Current Low, I
Input Capacitance
Setup Time, CMOS Data Input to CMOS_DCO
Hold Time, CMOS Data Input to CMOS_DCO
Output Voltage High, V
Output Voltage Low, V
Output Current High, I
Output Current Low, I
Maximum Clock Rate (CMOS_DCO)
CMOS_DCO to CMOS_FS Delay
Input Voltage Range, V
Input Differential Threshold, V
Input Differential Hysteresis, V
Input Differential Input Impedance, R
Maximum LVDS Input Rate
Setup Time, LVDS Differential Input Data to Differential DCOx
Hold Time, LVDS Differential Input Data to Differential DCOx
DCOP, FSP = V
Output Voltage High, V
Output Voltage Low, V
Output Differential Voltage, |V
Output Offset Voltage, V
Output Impedance, Single Ended, R
R
Change in |V
Change in V
Output Current—Driver Shorted to Ground, I
Output Current—Drivers Shorted Together, I
Power-Off Output Leakage, |I
Maximum Clock Rate (DCOP, DCON)
DCOx to FSx Delay
Differential Peak Voltage
Common-Mode Voltage
DAC Clock Rate
Maximum Clock Rate (f
Minimum Pulse Width High, t
Minimum Pulse Width Low, t
Minimum SDIO and CS to SCLK Setup, t
O
Mismatch Between A and B, ∆R
OS
OD
OA
Between 0 and 1, ∆V
| Between 0 and 1, |∆V
; DCON, FSN = V
IL
IL
IH
IH
OL
OL
OH
OA
IA
OH
OA
SCLK
OS
or V
or V
or V
, 1/t
IB
PWL
OB
XA
OB
3
PWH
IDTH
OD
IDTHH
SCLK
|, |I
OB
|
)
XB
; 100 Ω Termination
, V
O
OS
|
O
IDTHL
OD
IN
|
DS
1
SAB
SA
1
, I
SB
Rev. A | Page 5 of 76
2
2
Min
2.0
−10
−10
5.3
−1.4
2.4
0
0.28
825
−100
80
1.41
0.24
1025
150
1150
40
0.12
1.4
20
20
150
150
150
DAC
= 2.4 GHz, I
Typ
3.3
0
2
12
12
25
200
1.8
900
10
FS
= 20 mA, LVDS drivers and receivers
Max
250
25
0.8
+10
+10
3.3
0.4
0.85
1575
+100
120
1375
1250
140
10
25
25
20
4
10
0.37
2400
Unit
V
V
μA
μA
pF
ns
ns
V
V
mA
mA
MHz
ns
mV
mV
mV
Ω
MSPS
ns
ns
mV
mV
mV
mV
Ω
%
mV
mV
mA
mA
mA
MHz
ns
V
mV
MHz
MHz
ns
ns
ns
AD9789