AD9789 Analog Devices, AD9789 Datasheet - Page 34

• Manufacturer Part Number: AD9789
• Description: 14-Bit, 2400 MSPS RF DAC with 4-Channel Signal Processing
• Manufacturer: Analog Devices

Specifications of AD9789

• Resolution (bits): 14bit
• Dac Update Rate: 2.4GSPS
• Dac Settling Time: 13ns
• Max Pos Supply (v): +3.47V
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: LVDS,Par

AD9789
Table 32. Data Control Register (Address 0x21)
Bit
7
[6:5]
4
3
[2:0]
Table 33. DCO Frequency Register (Address 0x22)
Bit
7
[6:4]
[3:0]
Bit Name
BIN
BUSWDTH[1:0]
DATWDTH
CMPLX
Bit Name
Reserved
DCODIV[2:0]
ONES[3:0]
LTNCY[2:0]
Description
This bit selects the coding for the device.
0 = twos complement coding.
1 = straight binary coding.
These bits set the input data bus width for the device.
Setting
00
01
10
11
This bit sets the data-word width that is sent to the datapaths.
0 = 8-bit data-word.
1 = 16-bit data-word.
This bit configures the datapath for real or complex data.
0 = real data.
1 = complex data.
These bits set the turnaround latency from the FS pulse to the internal data sampling time. For more information,
see the Latency Register section.
Setting
000
001
…
111
Description
Reserved.
These bits configure the data clock output (DCO) frequency.
Setting
000
001
010
011
100
101
11x
These bits always read back 1111.
Input Bus Width
4 bits
8 bits
16 bits
32 bits
Latency
Input data begins to be sampled at approximately the first rising edge of DCO after FS
goes low.
Input data begins to be sampled at approximately the second rising edge of DCO after
FS goes low.
…
Input data begins to be sampled at approximately the eighth rising edge of DCO after
FS goes low.
DCO Clock Frequency
DCO clock disabled
f
f
Invalid
f
Invalid
Invalid
DACCLK
DACCLK
DACCLK
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/32
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Rev. A | Page 34 of 76