AD9789 Analog Devices, AD9789 Datasheet - Page 38

• Manufacturer Part Number: AD9789
• Description: 14-Bit, 2400 MSPS RF DAC with 4-Channel Signal Processing
• Manufacturer: Analog Devices

Specifications of AD9789

• Resolution (bits): 14bit
• Dac Update Rate: 2.4GSPS
• Dac Settling Time: 13ns
• Max Pos Supply (v): +3.47V
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: LVDS,Par

AD9789
Table 45. Mu Delay Control 3 Register (Address 0x39)
Bit
7
[6:5]
[4:0]
Table 46. Mu Delay Control 4 Register (Address 0x3A)
Bit
[7:0]
Table 47. Full-Scale Current 1 Register (Address 0x3C)
Bit
[7:0]
Table 48. Full-Scale Current 2 Register (Address 0x3D)
Bit
[7:2]
[1:0]
Table 49. Phase Detector Control Register (Address 0x3E)
Bit
7
6
5
4
[3:0]
Bit Name
MUDLY[0]
SEARCH_DIR[1:0]
MUPHZ[4:0]
Bit Name
MUDLY[8:1]
Bit Name
FSC[7:0]
Bit Name
Reserved
FSC[9:8]
Bit Name
PHZ_PD
Reserved
CMP_BST
AUTO_CAL
PHZ_DET_BIAS[3:0]
Description
This bit is the LSB of the mu delay value. Along with Bits[7:0] in Register 0x3A, this bit configures the
programmable mu delay; the search algorithm begins at this specified mu delay value. In manual mode, the
MUDLY bits can be written to. In tracking mode, the sampled MUDLY value can be read back. Even though
there are 9 bits of resolution for this delay line value, the maximum allowable mu delay is 431 (0x1AF). The
optimal point to begin the search is in the middle of the delay line, or approximately 216 (0xD8).
These bits configure the search direction, starting at the selected mu delay value.
00 = search down.
01 = search up.
10 = search up and down (optimal).
11 = invalid.
These bits specify the phase to be measured with the maximum allowable phase being 16 (10000). If a value
larger than 16 is loaded, the controller will not lock. When the desired phase is measured, the slope of the
phase measurement is calculated and compared to the configured slope, which is specified by the SLOPE bit
in Register 0x33[6]. For optimal ac performance, the best setting for the search is for a positive slope and a
phase value of 14 (01110).
Description
Along with Bit 7 in Register 0x39, these bits configure the programmable mu delay; the search algorithm
begins at this specified mu delay value. In manual mode, the MUDLY bits can be written to. In tracking mode,
the sampled MUDLY value can be read back. Even though there are 9 bits of resolution for this delay line
value, the maximum allowable mu delay is 431 (0x1AF). The optimal point to begin the search is in the
middle of the delay line, or approximately 216 (0xD8).
Description
Along with Bits[1:0] in Register 0x3D, this register sets the full-scale current for the DAC. For more information,
see the Voltage Reference section.
Setting (Includes Register 0x3D[1:0])
0000000000
…
1000000000
…
1011010000
…
1111111111
Description
Reserved.
Along with the FSC[7:0] bits in Register 0x3C, these bits set the full-scale current for the DAC. For more infor-
mation, see Table 47 and the Voltage Reference section.
Description
Powers down the phase detector. This bit is for factory use only; this bit should be set to 0.
Reserved.
Comparator boost. This bit is for factory use only; this bit should always be set to 1.
This bit is for factory use only; this bit should always be set to 1.
These bits display the binary weighted current. Do not write to these bits (factory use only).
Rev. A | Page 38 of 76
Full-Scale Current (mA)
8.6
…
20 (default)
…
25
…
32.1