AD9789 Analog Devices, AD9789 Datasheet - Page 49

• Manufacturer Part Number: AD9789
• Description: 14-Bit, 2400 MSPS RF DAC with 4-Channel Signal Processing
• Manufacturer: Analog Devices

Specifications of AD9789

• Resolution (bits): 14bit
• Dac Update Rate: 2.4GSPS
• Dac Settling Time: 13ns
• Max Pos Supply (v): +3.47V
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: LVDS,Par

D[31:0]
Design Example
In this example, a system has a DAC rate of 1600 MHz and a
baud rate of 15 MHz. Because f
ratio of f
between 0.5 and 1.0, an additional interpolation factor of 8×
must be applied, so N = 3. Solving for P/Q results in 5/6.
Therefore, three out of every 20 DCO clock edges should
result in data samples being loaded into the device (the ratio
of f
illustrates the operation of the interface in this example. In the
timing diagram, t
between the rising edge of FS and when the first sample in a
given transmission is sampled into the AD9789. Note that t
can vary by more than 1 DCO cycle.
Retimer Operation
The AD9789 uses a three-register retimer. The first two registers
are clocked from any one of 16 phases derived from the DAC
clock. The clock for the last register is fixed to Phase 15. The
programmable register clocks are the digital sample clock (DSC)
and the synchronizer clock (SNC). By choosing different
phases, fine adjustment of the sampling time can be made to
adjust for delays in the data source. Register 0x23[7:4] sets the
DSC phase (DSCPHZ) and Register 0x23[3:0] sets the SNC
phase (SNCPHZ) to any one of the 16 phases. The last register
in the chain is always clocked from Phase 15.
The parity counters can aid in identifying the edges of the data
valid windows. Operation in CMOS mode is quite similar to oper-
ation in LVDS mode, as can be seen in Figure 97 and Figure 98.
Φ 0 TO 15
Φ 0 TO 13
DCO
DSC
FS
FS
CMOS
/f
DATA
Φ 15
DSC
SNC
PHZ
DCO
DCO
= 3/20). Figure 96 shows a timing diagram that
t
PD
/f
FS
= 6.667. To satisfy the requirement that P/Q be
Figure 97. CMOS Retiming Registers
PD
32
corresponds to the propagation delay
SAMPLE
D
0
CLK
7 DCO CYCLES
Q
32
DCO
Figure 96. QDUC Mode Interface Timing Diagram for Design Example When FS Is Active
D
CLK
= f
Q
DAC
32
/16 = 100 MHz, the
D
CLK
Q
t
PD
BITS
0 TO 31
PD
Rev. A | Page 49 of 76
SAMPLE
6 DCO CYCLES
1
Register 0x23 and Register 0x21[2:0] can provide timing adjust-
ments with very low jitter penalty, but they can also be set to the
following recommended safe values:
•
•
Timing adjustments can then be made in an FPGA or other
data source.
Note that selecting Phase 14 or Phase 15 for SNCPHZ results in
a timing violation. In CMOS mode, setting DSCPHZ one step
behind or at SNCPHZ also results in a timing violation.
Latency Register
A latency register, controlled via Register 0x21[2:0], follows the
three-register retimer and can delay the data up to seven DCO
clocks in steps of one DCO clock. The critical retiming is
already done in the first three registers, so an incorrect latency
value does not result in a timing violation. The latency value
determines which data sample is the first sample in a trans-
mission and routes that sample to the appropriate channel.
Latency is affected by the round-trip delay from when FS goes
high to when the first data sample is output from the retimer. If
the latency value programmed into the part is incorrect, the
input data samples will not be assembled properly.
Φ 0 TO 15
Φ 0 TO 13
LVDS
DATA
In LVDS mode, DSCPHZ = 0, SNCPHZ = 3, LTNCY = 0
(see the Latency Register section)
In CMOS mode, DSCPHZ = 0, SNCPHZ = 7, LTNCY = 0
(see the Latency Register section)
Φ 15
DSC
SNC
PHZ
16
Figure 98. LVDS Rearranges the DSC Register
D
CLK
Q
t
PD
16
D
D
CLK
CLK
Q
Q
16
16
SAMPLE
2
D
D
CLK
CLK
7 DCO CYCLES
Q
Q
16
16
D
D
CLK
CLK
Q
Q
AD9789
BITS
0 TO 15
BITS
16 TO 31