AD9789 Analog Devices, AD9789 Datasheet - Page 29

• Manufacturer Part Number: AD9789
• Description: 14-Bit, 2400 MSPS RF DAC with 4-Channel Signal Processing
• Manufacturer: Analog Devices

Specifications of AD9789

• Resolution (bits): 14bit
• Dac Update Rate: 2.4GSPS
• Dac Settling Time: 13ns
• Max Pos Supply (v): +3.47V
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: LVDS,Par

SPI REGISTER DESCRIPTIONS
Table 12. SPI Control Register (Address 0x00)
Bit
7
6
5
4
[3:0]
Table 13. Saturation Counter Register (Address 0x01)
Bit
[7:0]
Table 14. Parity Counter Register (Address 0x02)
Bit
[7:0]
Table 15. Interrupt Enable Register (Address 0x03)
Bit
7
6
5
4
3
2
1
0
Bit Name
SDIO_DIR
LSBFIRST
RESET
LNG_INST
Bit Name
SATCNT[7:0]
Bit Name
PARCNT[7:0]
Name
PARERR
BISTDONE
PARMSET
PARMCLR
LOCKACQ
LOCKLOST
SATERR
Reserved
Description
This bit configures the SDIO pin as an input-only pin or as a bidirectional input/output pin. Both choices conform
to the SPI standard.
0 = input only.
1 = bidirectional (input/output).
This bit configures the SPI interface for MSB first or LSB first mode. Both choices conform to the SPI standard.
0 = MSB first.
1 = LSB first.
When set to 1, this bit resets the part. After the part is reset, 0 is written to this bit on the next cycle.
0 = no reset.
1 = software reset.
This bit sets the SPI to long instruction mode; 1 is the only valid value.
These bits should mirror Bits[7:4]. Bit 3 should mirror Bit 4, Bit 2 should mirror Bit 5, Bit 1 should mirror Bit 6, and
Bit 0 should mirror Bit 7.
Description
Setting this bit to 1 enables a PARERR flag to generate an interrupt request. Generating an interrupt request
results in Interrupt Bit 7 being set in Register 0x04 and the IRQ pin going low.
Setting this bit to 1 enables a BISTDONE flag to generate an interrupt request. Generating an interrupt request
results in Interrupt Bit 6 being set in Register 0x04 and the IRQ pin going low.
Setting this bit to 1 enables a PARMS_SET flag to generate an interrupt request. Generating an interrupt request
results in Interrupt Bit 5 being set in Register 0x04 and the IRQ pin going low.
Setting this bit to 1 enables a PARMS_CLR flag to generate an interrupt request. Generating an interrupt request
results in Interrupt Bit 4 being set in Register 0x04 and the IRQ pin going low.
Setting this bit to 1 enables a LOCKACQ flag to generate an interrupt request. Generating an interrupt request
results in Interrupt Bit 3 being set in Register 0x04 and the IRQ pin going low.
Setting this bit to 1 enables a LOCKLOST flag to generate an interrupt request. Generating an interrupt request
results in Interrupt Bit 2 being set in Register 0x04 and the IRQ pin going low.
Setting this bit to 1 enables a SATERR (overflow into 16× interpolator) flag to generate an interrupt request.
Generating an interrupt request results in Interrupt Bit 1 being set in Register 0x04 and the IRQ pin going low.
Reserved.
Description
This read-only register contains the saturation counter. This register reflects the number of samples at the output of
the SUMSCALE gain block that overrange the datapath and are digitally clipped. The count is cleared by writing
a 1 to Register 0x04, Bit 1.
Description
This read-only register contains the input data parity error counter. The count is cleared by writing a 1 to
Register 0x04, Bit 7.
Rev. A | Page 29 of 76
AD9789