AD9789 Analog Devices, AD9789 Datasheet - Page 53

• Manufacturer Part Number: AD9789
• Description: 14-Bit, 2400 MSPS RF DAC with 4-Channel Signal Processing
• Manufacturer: Analog Devices

Specifications of AD9789

• Resolution (bits): 14bit
• Dac Update Rate: 2.4GSPS
• Dac Settling Time: 13ns
• Max Pos Supply (v): +3.47V
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: LVDS,Par

LVDS Interface Timing
When the AD9789 is configured with an LVDS interface
(CMOS_CTRL = CMOS_BUS = 0 V), an LVDS data clock out-
put signal, DCO, is provided to drive data from the data source.
The LVDS interface may be single data rate (SDR) or double
data rate (DDR) depending on the bus width configuration. In
SDR, data is sampled into the part only on the falling edge of
the internal sampling clock (DSC). Note that the frequency of
DCO is equal to the frequency of DSC, so the effective data rate
is equal to the DCO frequency. The phase relationship between
DCO and DSC is determined by DSCPHZ (Register 0x23[7:4]).
In DDR, data is sampled into the part on both the rising and falling
edges of DSC, so the effective data rate is equal to twice the DCO
frequency. The interface is DDR only when the bus width is equal to
32 bits. The DCO frequency is equal to f
The timing of the input data is referenced to DCO for a given phase
of DSC. The LVDS input data timing over temperature is shown
in Table 70 for DCO_INV = 0 (Register 0x20[4]), DSCPHZ = 0
(Register 0x23[7:4]), and DCODIV = 1 (Register 0x22[6:4]).
Table 70. LVDS Data Input Timing with Respect to DCO
Temperature
−40°C
+25°C
+85°C
−40°C to +85°C
In DDR mode, these setup and hold times must be applied to
both edges of DCO. In SDR mode, these setup and hold times
must be applied to the falling edge of DCO.
For any value of DSCPHZ greater than 0, the setup and hold
times shift by increments of t
of the data clock.
INPUT
INPUT
DATA
DATA
DCO
DCO
DSC
DSC
t
t
S
H
= 1.41 ns − ((t
= 0.24 ns + ((t
t
S
Figure 102. LVDS Input Timing, SDR vs. DDR
t
H
DCO
Min t
1.04
1.23
1.41
1.41
DCO
DOUBLE DATA RATE (DDR)
/16) × DSCPHZ)
SINGLE DATA RATE (SDR)
/16) × DSCPHZ)
S
(ns)
DCO
/16, where t
t
t
S
Min t
0.24
0.16
0.03
0.24
S
DAC
t
t
H
H
H
/16 when DCODIV = 1.
(ns)
DCO
is the period
Min DVW (ns)
1.28
1.39
1.44
1.65
t
S
t
Rev. A | Page 53 of 76
H
In some interface modes, the delay from the rising edge of
DCO to the rising edge of FS needs to be known. This delay
is summarized over temperature in Table 71.
Table 71. Timing Delay Between LVDS DCO and FS
Temperature
−40°C
+25°C
+85°C
−40°C to +85°C
Parity
The AD9789 supports parity checking on the input data bus.
There are three parity checking modes: even parity, odd parity,
and IQ parity. In IQ parity mode, a value of 0 is always expected
on the I channel and a value of 1 is always expected on the Q
channel. Note that IQ parity mode is generally useful only when
the LVDS interface is used. These modes are controlled via
Register 0x20[1:0].
Table 72. Parity Mode SPI Settings
Parity Mode
Deactivates Parity Checking
IQ Parity
Even Parity
Odd Parity
If parity checking is used, each data-word that is transferred
into the AD9789 should have a parity bit accompanying it,
regardless of FS. In other words, parity must be valid for every
DCO edge. The parity bits are located at Pin L4 and Pin M4.
When operating the interface in CMOS mode, the input parity
bits are referred to as P1 and P0, respectively. When operating
the interface in LVDS mode, the input parity bits are referred
to as PARP and PARN, respectively.
Recall that the LVDS interface can be single data rate (SDR) or
double data rate (DDR), depending on the bus width configu-
ration. The interface is DDR only when the bus width is equal
to 32 bits.
DCO
DSC
FS
t
D
Figure 103. LVDS DCO to FS Delay
t
0.37
0.35
0.32
0.37
D, MAX
DCO to FS (ns)
Register 0x20[1:0]
00
01
10
11
t
0.21
0.16
0.12
0.12
D, MIN
DCO to FS (ns)
AD9789