AD9789 Analog Devices, AD9789 Datasheet - Page 48

• Manufacturer Part Number: AD9789
• Description: 14-Bit, 2400 MSPS RF DAC with 4-Channel Signal Processing
• Manufacturer: Analog Devices

Specifications of AD9789

• Resolution (bits): 14bit
• Dac Update Rate: 2.4GSPS
• Dac Settling Time: 13ns
• Max Pos Supply (v): +3.47V
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: LVDS,Par

AD9789
Pin Mapping in QDUC Mode
In CMOS mode, the AD9789 input pins are mapped as shown
in Table 64.
Table 64. Pin Mapping in QDUC Mode for CMOS Interface
Data Bit
D31
D16
D15
D0
P1
P0
In LVDS mode, the AD9789 input pins are mapped as shown in
Table 65.
Table 65. Pin Mapping in QDUC Mode for LVDS Interface
Data Bit
D15P, D15N rising
D0P, D0N rising
D15P, D15N falling
D0P, D0N falling
PARP, PARN rising
PARP, PARN falling
1
G
M
“Rising” means that the data is sourced on the rising edge of DCOx; “falling”
means that the data is sourced on the falling edge of DCOx.
A
B
C
D
E
H
K
N
F
L
P
J
1
2
3
P1
P0
Figure 94. CMOS Data Input Pin Mapping
4
D[31:0] CMOS DATA INPUTS
PARITY AND CONTROL INPUTS
30 26 22 18 14 10
29 25 21 17 13
28 24 20 16 12
31 27 23 19 15 11
5
6
Description
MSB of I data
LSB of I data
MSB of Q data
LSB of Q data
Parity for D[15:0]P, D[15:0]N
rising
Parity for D[15:0]P, D[15:0]N
falling
Description
MSB of I data
LSB of I data
MSB of Q data
LSB of Q data
Parity for D[31:16]
Parity for D[15:0]
7
8
9
10
9
8
11
4
7
6
5
12
1
0
3
2
13
1
BU
DC
CT
FS
4
CMOS_BUS
CMOS_CTRL
CMOS_FS
CMOS_DCO
Pin No.
L5, M5
N12, P12
L5, M5
N12, P12
L4, M4
L4, M4
Pin No.
L5
P8
L9
P12
L4
M4
Rev. A | Page 48 of 76
1
PARN
DCO and FS Rates in QDUC Mode
In QDUC mode, DCODIV should always be set to 1 (Register
0x22[6:4] = 001). The clock period of DCO is equal to 16 DAC
clock periods. When only 16× interpolation is required and the
rate converter is not used, the data rate of the interface is equal
to f
If further interpolation or rate conversion is enabled in the
datapath, the data rate of the interface is f
of FS, f
specified by the following equation:
where:
N is the number of 2× interpolation filters enabled.
P/Q is the rate converter ratio.
The FS signal becomes a request for data that effectively gates the
DCO clock and ensures that data is sent at the correct baud rate.
If P/Q = 1 and N = 0, DCO occurs at the baud rate and FS is not
required. In this case, FS is inactive (always high). The DCO
signal can be used as a constant rate clock to request samples
from the data source.
PARP
DCO
f
M
B
C
D
G
H
K
N
A
E
F
P
J
L
.
BAUD
FS
, is equal to the baud rate, f
1
=
2
2
Figure 95. LVDS Data Input Pin Mapping
N
f
DCO
3
×
Q
P
P+
P–
4
14
15 13 11
15 13 11
14 12 10
14 12 10
5
+LVDS
6
7
14 –LVDS
8
9
9
8
8
BAUD
6
6
9
7
7
10
. The baud rate can be
5
5
4
4
BAUD
11
3
3
2
2
. The average rate
12
1
1
0
0
13
DC
DC
FS
FS
1
4
FSP
FSN
DCOP
DCON