AD9789 Analog Devices, AD9789 Datasheet - Page 42

• Manufacturer Part Number: AD9789
• Description: 14-Bit, 2400 MSPS RF DAC with 4-Channel Signal Processing
• Manufacturer: Analog Devices

Specifications of AD9789

• Resolution (bits): 14bit
• Dac Update Rate: 2.4GSPS
• Dac Settling Time: 13ns
• Max Pos Supply (v): +3.47V
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: LVDS,Par

AD9789
Sample Rate Converter
The purpose of the sample rate converter (SRC) is to provide
increased flexibility in the ratio of the input baud rate to the
DAC update rate. Each of the four channelization datapaths
contains a sample rate converter (SRC) that provides a data rate
conversion in the range of 0.5 to 1.0 inclusive. The rate conversion
factor is set by the ratio of two 24-bit values, P and Q. Figure 83
is a conceptual block diagram of the SRC. It can be thought of
as an interpolation block, followed by filtering and decimation
blocks.
The values of P and Q are set by programming the P[23:0] and
Q[23:0] registers at Address 0x16 through Address 0x1B.
Table 51. Register Locations for Sample Rate Converter
Bits
[23:16] (Byte 2)
[15:8] (Byte 1)
[7:0] (Byte 0)
The values of P and Q should be selected to satisfy the following
equation for the desired baud rate (f
quency (f
where I is the total interpolation ratio of the SRRC filter and the
five half-band interpolation filters.
If Equation 1 is satisfied, the long-term baud rate, f
exactly maintained. No residual frequency offset errors are
introduced by the rate conversion process.
The values of P and Q must be selected within the following
constraints:
Equation 3 states that the value of Q must be shifted so that the
MSB of Q is set.
In most systems, the baud rate is a given, and the DAC sample
rate is selected so that it is high enough to support the signal
bandwidth and output frequency requirements. In many cases,
it is desirable to set the DAC clock rate to a multiple of a system
clock rate. The following example shows how P and Q can be
selected in such a system.
Figure 83. Conceptual Block Diagram of the Sample Rate Converter
Q[23] = 1
0
f
5 .
DAC
≤
DAC
=
Q
P
).
I
≤
×
1
Q
P
0 .
×
P
P
16 ×
24
Numerator (P)
Register 0x1B
Register 0x1A
Register 0x19
f
BAUD
BAUD
) and DAC clock fre-
Q
Q
24
Denominator (Q)
Register 0x18
Register 0x17
Register 0x16
BAUD
, is
Rev. A | Page 42 of 76
(1)
(2)
(3)
Example
A DOCSIS application has a master system clock that runs at a
frequency of f
all of which are fractions of the master clock and can be
represented by the following equation:
Equation 1 must be satisfied for f
To facilitate this, the DAC sampling frequency is selected to be a
multiple of f
frequency requirements. For f
width requirement of 32 MHz or greater, and a supported output
frequency band of up to 1 GHz, the following DAC sampling
frequency can be selected:
Inserting Equation 4 and Equation 5 into Equation 1 results in
Equation 6.
Enabling the SRRC filter and four of the half-band interpolation
filters would result in the total interpolation factor, I, being equal
to 32. Substituting 32 for I and simplifying Equation 6 results in
Equation 7.
Recall that N and M are given by the required baud rate. For
example, assume a baud rate of 5.0569 MHz, which results from
M = 401 and N = 812.
P and Q can then be calculated from the numerator and
denominator of Equation 9.
Because the value of Q must be MSB justified, both numbers
can be shifted by 11 bits, resulting in the final P and Q values
of 0xB1A000 and 0xC80000, respectively.
Baseband Digital Upconverter
The digital upconverter enables each baseband channel to be
placed anywhere from dc to f
each of the four channels is register programmable through the
24-bit frequency tuning words, FTW 0 through FTW 3. For the
desired center frequency of each individual channel, the FTW
can be calculated as follows:
224
FTW
Q
Q
f
P
f
P
f
DAC
BAUD
BAUD
=
=
×
812
M
401
N
=
f
=
=
=
MASTER
MASTER
224
×
⎛
⎜
⎝
812
MASTER
401
×
f
M
N
16
CENTER
f
7
16
16
DAC
×
7
×
×
that satisfies the signal bandwidth and output
f
=
=
. Several channel baud rates are supported,
f
MASTER
10
⎞
⎟
⎠
MASTER
I
5684
6416
×
.
×
24
(
2
Q
P
MHz
24
=
×
=
−
16
2293
MASTER
DAC
x 0
x 0
1
)
×
=
1634
1910
/16. The center frequency for
BAUD
. 5
M
.
N
76
0569
= 10.24 MHz, a signal band-
×
MHz
to be exactly maintained.
f
MASTER
MHz
(4)
(5)
(6)
(7)
(8)
(9)