AD9789 Analog Devices, AD9789 Datasheet - Page 58

• Manufacturer Part Number: AD9789
• Description: 14-Bit, 2400 MSPS RF DAC with 4-Channel Signal Processing
• Manufacturer: Analog Devices

Specifications of AD9789

• Resolution (bits): 14bit
• Dac Update Rate: 2.4GSPS
• Dac Settling Time: 13ns
• Max Pos Supply (v): +3.47V
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: LVDS,Par

AD9789
Optimizing the Clock Common-Mode Voltage
In addition to the system that optimizes the handoff timing, an
additional system sets the common-mode voltage of the clock.
This system can be used to properly align the crossing point of
the CLKP and CLKN signals to ensure that the duty cycle of the
clock is set properly. Figure 115 shows how the common-mode
voltage of CLKP and CLKN is set. There are eight switches
controlled by the CLKP_CML bits (Register 0x32[4:1]) and the
CLKN_CML bits (Register 0x31[7:4]) for both the CLKP and
CLKN signals. The direction of the adjustment is determined by
the PSIGN and NSIGN bits (Register 0x32, Bit 5 and Bit 0). If
PSIGN and NSIGN are low, the common-mode voltage decreases
with CLKP_CML/CLKN_CML values. If PSIGN and NSIGN are
high, the common-mode voltage increases with CLKP_CML/
CLKN_CML values, as shown in Figure 116. With both
CLKP_CML and CLKN_CML set to 0, the feedback path forces
the common-mode voltage to be set to approximately 0.9 V. The
optimal ac performance occurs at a setting of −15 on both the
CLKP and CLKN offset bits.
Clock Phase Noise Effects on AC Performance
The quality of the clock source driving the ADCLK914 deter-
mines the achievable ACLR performance of the AD9789.
Table 76 summarizes the close-in ACLR for a four-carrier
DOCSIS signal at 900 MHz with respect to various phase
noise profiles. (All ACLR values are specified in dBc.)
Figure 116. Common-Mode Voltage with Respect to CLKP_CML/CLKN_CML
1.10
1.05
1.00
0.95
0.90
0.85
0.80
0.75
0.70
–15 –13 –11 –9 –7 –5 –3 –1
CLKx_CML
CLKx_CML
CLKP/CLKN
SIGN = 0
SIGN = 1
Figure 115. Clock Common-Mode Control
CLKP
and PSIGN/NSIGN
CVDD18
CLKN
OFFSET CODE
1
3
5
7
9
11 13 15
Rev. A | Page 58 of 76
Table 76. Four-Carrier DOCSIS Close-In ACLR Performance
at 900 MHz for Various Phase Noise Profiles
Band
750 kHz
to 6 MHz
6 MHz to
12 MHz
12 MHz to
18 MHz
Table 77 shows the phase noise at various offsets for each
profile. (All phase noise numbers are specified in dBc/Hz.)
Table 77. Phase Noise Summary for Each Profile
Offset
2 kHz
20 kHz
200 kHz
2 MHz
20 MHz
1
To meet the close-in ACLR requirements for four-carrier
DOCSIS, the phase noise found in Profile 3 is the minimum
requirement necessary.
MU DELAY CONTROLLER
The mu delay adjusts timing between the digital and analog
blocks. The mu delay controller receives phase relational
information between the digital and analog clock domains. The
control system continuously adjusts the mu delay to maintain
the desired phase relationship between the digital and analog
sections. A top level diagram of the mu delay within the DAC is
shown in Figure 117.
The mu controller has two modes of operation: initial phase
search and phase tracking. In the phase search mode, the con-
troller looks for the initial mu delay value to use before going
into tracking mode. In tracking mode, the controller makes
adjustments to the initial mu delay value to keep the phase at
the desired value. The initial phase search is required because
multiple mu delay settings may result in the desired phase, but
the device may not operate correctly at all of those mu delay values.
At offsets less than 500 kHz, the measurement instrument dominates the
phase noise performance.
1
CLOCK
16-BIT
DATA
DAC
Profile 1
−71
−70.9
−71
Profile 1
−114.8
−117.8
−128.3
−148.5
−152.5
Figure 117. Mu Delay Controller Block Diagram
16
Profile 2
−67.2
−70.3
−70.8
DELAY
MU
Profile 2
−112.8
−115.5
−118.9
−127.9
−149.9
Phase Noise (dBc/Hz)
CIRCUITRY
Phase Noise (dBc)
CONTROL
DIGITAL
MU Φ
Profile 3
−62.4
−67
−70.8
Φ DET
MU
14
Profile 3
−111.7
−114.6
−118.3
−122.2
−148
2.4GSPS
14-BIT
DAC
Profile 4
−59.1
−63.8
−70.8
Profile 4
−111.2
−113.8
−116.8
−117.9
−145.7
Spec
−60
−63
−65