AD9789 Analog Devices, AD9789 Datasheet - Page 52

• Manufacturer Part Number: AD9789
• Description: 14-Bit, 2400 MSPS RF DAC with 4-Channel Signal Processing
• Manufacturer: Analog Devices

Specifications of AD9789

• Resolution (bits): 14bit
• Dac Update Rate: 2.4GSPS
• Dac Settling Time: 13ns
• Max Pos Supply (v): +3.47V
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: LVDS,Par

AD9789
Delay
LAT
SNC
DSC
Delay
LAT
SNC
DSC
Delay
LAT
SNC
DSC
Delay
LAT
SNC
DSC
Delay
LAT
SNC
DSC
Delay
LAT
SNC
DSC
Latency Effects on Channelizer Mode
When selecting an interface configuration in channelizer mode,
the number of DCO cycles between FS pulses (cycles
be greater than the number of DCO cycles required by the inter-
face configuration (cycles
these available DCO cycles between FS. This decrease in available
DCO cycles is a result of the round-trip propagation delay from
the FS output of the AD9789 to the respective data sample at the
input of the AD9789 (LTNCY[2:0]) in addition to the internal
latency of the device.
For a successful interface design, the following condition must
be met:
CMOS Interface Timing
When the AD9789 is configured with a CMOS interface
(CMOS_CTRL = CMOS_BUS = 3.3 V), a CMOS data clock
output signal, DCO, is provided to drive data from the data
source. The output signal operates at the input data rate, which
is equal to f
sampled on the rising edge of an internal sampling clock (DSC).
Note that the frequency of DCO is equal to the frequency of
DSC and the phase relationship between DCO and DSC is
determined by DSCPHZ (Register 0x23[7:4]).
cycles
AVAIL
72
5
3
8
80
5
7
0
88
6
3
8
96
6
7
0
104
7
3
8
112
7
7
0
DAC
/16 when DCODIV = 1. CMOS data on the bus is
≥ cycles
73
5
4
9
81
5
8
1
89
6
4
9
97
6
8
1
105
7
4
9
113
7
8
1
INTERFACE
74
5
4
10
82
5
8
2
90
6
4
10
98
6
8
2
106
7
4
10
114
7
8
2
INTERFACE
+ LTNCY[2:0] + 2
75
5
5
11
83
5
9
3
91
6
5
11
99
6
9
3
107
7
5
11
115
7
9
3
). Latency consumes some of
76
5
5
12
84
5
9
4
92
6
5
12
100
6
9
4
108
7
5
12
116
7
9
4
77
5
6
13
85
5
2
5
93
6
6
13
101
6
2
5
109
7
6
13
117
7
2
5
78
5
6
14
86
6
2
6
94
6
6
14
102
7
2
6
110
7
6
14
X
X
X
X
AVAIL
) must
79
5
7
15
87
6
3
7
95
6
7
15
103
7
3
7
111
7
7
15
X
X
X
X
Rev. A | Page 52 of 76
The timing of the input data is referenced to DCO for a given
phase of DSC. The CMOS data input timing over temperature is
shown in Table 68 for DCO_INV = 0 (Register 0x20[4]),
DSCPHZ = 0 (Register 0x23[7:4]), and DCODIV = 1 (Register
0x22[6:4]). Table 68 also shows the data valid window (DVW).
The data valid window is the sum of the setup and hold times of
the interface. DVW is the minimum amount of time that valid
data must be presented to the device to ensure proper sampling.
Table 68. CMOS Data Input Timing with Respect to DCO
Temperature
−40°C
+25°C
+85°C
−40°C to +85°C
For any value of DSCPHZ greater than 0, the setup and hold
times shift by increments of t
the data clock.
In some interface modes, the delay from the rising edge of DCO
to the rising edge of FS needs to be known. This delay is summa-
rized over temperature in Table 69.
Table 69. Timing Delay Between CMOS_DCO and CMOS_FS
Temperature
−40°C
+25°C
+85°C
−40°C to +85°C
INPUT
DCO
DSC
DATA
DCO
DSC
FS
t
t
S
H
= 5.3 ns − ((t
= 0.24 ns + ((t
Figure 101. CMOS_DCO to CMOS_FS Delay
t
D
t
0.64
0.71
0.85
0.85
Figure 100. CMOS Input Timing
D, MAX
DCO
Min t
4.9
5.1
5.3
5.3
DCO
/16) × DSCPHZ)
/16) × DSCPHZ)
DCO to FS (ns)
S
(ns)
DCO
t
S
/16, where t
Min t
−1.4
−1.6
−1.7
−1.4
t
H
H
(ns)
t
0.28
0.4
0.49
0.28
D, MIN
DCO
is the period of
DCO to FS (ns)
Min DVW (ns)
3.5
3.5
3.6
3.9