AD9789 Analog Devices, AD9789 Datasheet - Page 43

• Manufacturer Part Number: AD9789
• Description: 14-Bit, 2400 MSPS RF DAC with 4-Channel Signal Processing
• Manufacturer: Analog Devices

Specifications of AD9789

• Resolution (bits): 14bit
• Dac Update Rate: 2.4GSPS
• Dac Settling Time: 13ns
• Max Pos Supply (v): +3.47V
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: LVDS,Par

The calculated FTW for each channel should be entered into
the register locations listed in Table 52.
Table 52. Register Locations of FTWs for Each Channel
FTW
[23:16]
[15:8]
[7:0]
The FTW sets the frequency of the sine and cosine signals
generated by the numerically controlled oscillator (NCO).
The complex output from the NCO is multiplied by the input
datapath signal to modulate the signal to the desired output
frequency. A conceptual block diagram of the baseband digital
upconverter is shown in Figure 84.
Individual Channel Scalar
The last block in the datapath is an 8-bit scalar (Register 0x25 to
Register 0x28) intended for compensating out any sampling and
hardware roll-offs that may be encountered. The scale factor
applied to each channel is calculated as follows:
The range of the channel gain is 0 to 1.9921875 with a step size
of 0.0078125. An individual channel can be easily and quickly
muted, if desired, by setting the scale factor to 0.
Table 53. Register Locations for Channel Gain Scalar
CHANxGAIN
[7:0]
The default value of the channel gain provides a scale factor of
1. As shown in Figure 85, the output of the input scalar block is
rounded to the nearest 16-bit value. If the output exceeds the
maximum or minimum value, it is clipped to either positive or
negative full scale (0x7FFF or 0x8000).
Figure 84. Conceptual Block Diagram of the Baseband Digital Upconverter
ScaleFacto =
Channel 0
Reg. 0x0C
Reg. 0x0B
Reg 0x0A
Figure 85. Individual Channel Gain Control
Channel 0
Reg. 0x25
r
CHANxGAIN[7:0]
CHANxGAIN[
FTW NCO FREQUENCY
8
TUNING WORD
Channel 1
Reg. 0x0F
Reg. 0x0E
Reg 0x0D
128
Channel 1
Reg. 0x26
COS
SIN
SATURATE
24
ROUND
7
:0]
Channel 2
Reg. 0x12
Reg. 0x11
Reg 0x10
Channel 2
Reg. 0x27
Channel 3
Reg. 0x15
Reg. 0x14
Reg 0x13
Channel 3
Reg. 0x28
Rev. A | Page 43 of 76
DIGITAL BLOCK UPCONVERTER
The second half of the DSP engine on the AD9789 combines the
outputs of the four datapaths into one block, scales the block of
channels, interpolates by 16× to the full DAC rate, and performs
a band-pass filter operation allowing the block of channels to be
placed anywhere in the Nyquist bandwidth of the DAC.
Each block of the digital block upconverter is described in more
detail in the following sections.
Summing Junction Scalar
The summing junction scalar block operates on the sum of the
four channels. The value of SUMSCALE[7:0] is programmed in
Register 0x08. The scale factor applied to the data is calculated
as follows:
This factor provides a scaling range of the input data from 0 to
3.984375 with a step size of 0.015625. The default value of 0x0D
provides a scale factor of 0.203125. Note that when the channels
are summed, they are clipped at the output of the summing
junction scalar block if the value exceeds the maximum or
minimum full-scale value (0x7FFF or 0x8000). If the full 16-bit
range of each individual channel is used, the sum scalar should
be set to 0x10 (0.25) to avoid the possibility of clipping.
In practice, the signal-to-noise ratio (SNR) of the channel can
be improved by increasing the sum scale factor and permitting
a small amount of clipping. The larger signal amplitude can
improve the SNR if the clipping is brief and infrequent.
Figure 86. Functional Block Diagram of the Digital Block Upconverter
ScaleFacto =
Figure 87. Block Diagram of the Summing Junction Scalar
DATA-
DATA-
DATA-
DATA-
PATH
PATH
PATH
PATH
0
1
2
3
r
SUMSCALE[7
REGISTER 0x08
SCALE
SUMSCALE
SUM
DIGITAL BLOCK
UPCONVERTER
64
TO SATURATION COUNTER
8
REGISTER 0x03[1]
SATURATE
:0]
SATERR
ROUND
f
C
f
DAC/2
BPF
BPF
= 0 TO
f
C
AD9789