AD9789 Analog Devices, AD9789 Datasheet - Page 35

• Manufacturer Part Number: AD9789
• Description: 14-Bit, 2400 MSPS RF DAC with 4-Channel Signal Processing
• Manufacturer: Analog Devices

Specifications of AD9789

• Resolution (bits): 14bit
• Dac Update Rate: 2.4GSPS
• Dac Settling Time: 13ns
• Max Pos Supply (v): +3.47V
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: LVDS,Par

Table 34. Internal Clock Phase Adjust Register (Address 0x23)
Bit
[7:4]
[3:0]
Table 35. Parameter Update Register (Address 0x24)
Bit
7
[6:0]
Table 36. Channel Gain Registers (Address 0x25 to Address 0x28)
Address
0x25
0x26
0x27
0x28
Table 37. Spectrum Shaping Register (Address 0x29)
Bit
[7:1]
0
Bit Name
DSCPHZ[3:0]
SNCPHZ[3:0]
Name
PARMNEW
Reserved
Name
Reserved
SPEC_INV
Register Name
Channel 0 gain
Channel 1 gain
Channel 2 gain
Channel 3 gain
Description
The data sampling clock (DSC) is an internal clock that is used to sample the input data. This clock can occur on
1 of 16 phases to optimize the setup and hold timing of the data interface.
Setting
0000
0001
…
1111
The synchronization clock (SNC) is an internal clock that is used to synchronize the digital datapath clock with
the DAC clock. This clock can occur on 1 of 16 phases to optimize the DAC-to-datapath timing.
Setting
0000
0001
…
1111
Description
This bit must transition from 0 to 1 for changes to Register 0x22 and Register 0x23 to take effect. Assuming that
this bit was previously set to 0, writing a 1 to this bit causes the readback value of the bit to reflect the state of
the chip. (The state of the chip is updated very quickly; for this reason, users with slow SPI implementations may
never read back a 0 after an update.)
0 = values have not been updated.
1 = values have been updated.
Reserved.
Description
Reserved.
Setting this bit to 1 spectrally inverts the signal, effectively multiplying the Q data by −1.
Bit Name
CHAN0GAIN[7:0]
CHAN1GAIN[7:0]
CHAN2GAIN[7:0]
CHAN3GAIN[7:0]
Selected Phase
Earliest clock phase
Second earliest clock phase that occurs 1/16 of a DSC cycle later
…
Last available clock phase
Selected Phase
Earliest clock phase
Second earliest clock phase that occurs 1/16 of a DSC cycle later
…
Last available clock phase
Description
These registers configure a value for the 1.7 multiplier applied to each individual
channel just prior to the SUMSCALE block. The range of the channel gain is 0 to
1.9921875 with a step size of 0.0078125. To mute an individual channel, set the
scale factor to 0.
Setting
00000000
00000001
…
11111111
Rev. A | Page 35 of 76
Channel Gain
0
0.0078125
…
1.9921875
AD9789