AD9789 Analog Devices, AD9789 Datasheet - Page 47

• Manufacturer Part Number: AD9789
• Description: 14-Bit, 2400 MSPS RF DAC with 4-Channel Signal Processing
• Manufacturer: Analog Devices

Specifications of AD9789

• Resolution (bits): 14bit
• Dac Update Rate: 2.4GSPS
• Dac Settling Time: 13ns
• Max Pos Supply (v): +3.47V
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: LVDS,Par

Before choosing an interface configuration, divide the frequency
of DCO by the highest frequency baud rate that will be used in
the system and truncate it. The result is the number of available
DCO cycles (cycles
Each interface configuration requires a particular number of
DCO cycles between FS pulses to successfully load data into all
channels. This number can be calculated using the following
formula:
where:
N is the number of channels enabled (1 to 4). N is always equal
to 4 if channel prioritization is set to 1 (see the Channel
Prioritization section).
F represents the data format. If the data format is real, F = 1;
if the data format is complex, F = 2.
DW is the data width in number of bits (8 or 16).
BW is the bus width in number of bits (4, 8, 16, or 32).
For a successful interface design, the number of DCO cycles
between FS pulses must be greater than the number of DCO
cycles required by the interface.
Design Example
In this example, a system has the baud rate f
4-bit-wide interface is desired for four channels with real data
format and a data width of 8 bits, the selected f
least 8 × f
interface speed with N = 1, P/Q = 0.7, and I = 32.
The f
number of available DCO cycles is reduced to 11; this option
may not be feasible when the latency values are taken into
account. See the Latency Effects on Channelizer Mode section
for more information about latency.
Channel Prioritization
When channels are enabled and disabled, the input interface
mapping can be affected. If channel prioritization (Register
0x20[2]) is set to 0, the device expects input samples for only
the channels that are enabled. In this configuration, the physical
channel mapping at the DUT input can move around based on
the number of channels enabled, where Channel 0 has highest
priority (it never moves location when enabled). If channel
prioritization is set to 1, data is expected for all four channels
but the data is ignored internally if the channel is disabled.
This method is recommended because enabling and disabling
channels does not shift the input data bus.
f
f
cycles
cycles
DCO
DAC
DCO
/f
= 32 × 0.7 × 16 × 6.4 MHz = 2293.76 MHz
= 2293.76 MHz/(16 × 1) = 143.36 MHz
FS
BAUD
AVAIL
INTERFACE
. First, using Equation 1 and Equation 2, evaluate the
ratio = 22.4. If a value of N = 2 is selected, the
=
floor
AVAIL
=
N
⎛
⎜
⎜
⎝
) between FS pulses.
×
max
F
f
×
DCO
f
DW
BW
BAUD
⎞
⎟
⎟
⎠
FS
= 6.4 MHz. If a
DCO
should be at
Rev. A | Page 47 of 76
If the number of channels enabled is always less than four and
the user does not plan to enable and disable channels dynamically,
setting channel prioritization to 0 is the best choice because
fewer clocks and/or pins are required to transfer the input data.
An example of channel prioritization set to 0 is shown in Table 62.
In this example, the data interface is configured for CMOS with
32-bit bus width, 8-bit data width, and real data format.
Table 62. Input Mapping vs. Enabled Channels,
Channel Prioritization = 0
Channels
4 Channels
Enabled
Channel 0
Disabled
Channel 0,
Channel 2
Disabled
The same example behaves differently when channel prioritization
is set to 1, as shown in Table 63.
Table 63. Input Mapping vs. Enabled Channels,
Channel Prioritization = 1
Channels
4 Channels
Enabled
Channel 0
Disabled
Channel 0,
Channel 2
Disabled
Quadrature Digital Upconverter (QDUC) Mode
In QDUC mode (Register 0x20[3] = 1), the data interface is fixed
at a 32-bit bus width, 16-bit data width, and complex data format.
In QDUC mode, only one channel should be enabled. If more
than one channel is enabled, identical I and Q data is sent to
each enabled channel. Within the datapath, the QAM mapper
and the SRRC filter must be bypassed (Register 0x06[7:6] = 11).
DCO
P0
P1
FS
INPUT
PINS
32
16 TO 31
0 TO 15
CMOS
CMOS
LVDS
LVDS
RISE
FALL
[D31:D24]
Channel 3
Channel 3
Channel 3
[D31:D24]
Channel 3
Q
I
Figure 93. QDUC Mode
[D23:D16]
Channel 2
Channel 2
[D23:D16]
Channel 2
Channel 3
I AND Q
16 BITS
I AND Q
16 BITS
I AND Q
16 BITS
I AND Q
16 BITS
CMOS Bit Mapping
CMOS Bit Mapping
OFF
OFF
OFF
ON
[D15:D8]
Channel 1
Channel 1
Channel 1
[D15:D8]
Channel 1
Channel 2
Channel 3
AD9789
[D7:D0]
Channel 0
[D7:D0]
Channel 0
Channel 1
Channel 1
f
0 TO
DAC
BPF
f
BPF
C
f
C
=
/2