p2125vps20 Renesas Electronics Corporation., p2125vps20 Datasheet - Page 121
p2125vps20
Manufacturer Part Number
p2125vps20
Description
16-bit Single-chip Microcomputer H8s Family / H8s/2100 Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.P2125VPS20.pdf
(700 pages)
- Current page: 121 of 700
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5.4
5.4.1
The interrupt sources of external interrupts are NMI and IRQ7 to IRQ0. These interrupts can be
used to restore this LSI from software standby mode.
(1)
The nonmaskable external interrupt NMI is the highest-priority interrupt, and is always accepted
regardless of the interrupt control mode or the status of the CPU interrupt mask bits. The NMIEG
bit in SYSCR can be used to select whether an interrupt is requested at a rising edge or falling
edge on the NMI pin.
(2)
Interrupts IRQ7 to IRQ0 are requested by an input signal at pins IRQ7 to IRQ0. Interrupts IRQ7 to
IRQ0 have the following features:
• The interrupt exception handling for interrupt requests IRQ7 to IRQ0 can be started at an
• Using ISCR, it is possible to select whether an interrupt is generated by a low level, falling
• Enabling or disabling of interrupt requests IRQ7 to IRQ0 can be selected with IER.
• The status of interrupt requests IRQ7 to IRQ0 is indicated in ISR. ISR flags can be cleared to 0
When the interrupts are requested while IRQ7 to IRQ0 interrupt requests are generated at low
level of IRQn input, hold the corresponding IRQ input at low level until the interrupt handling
starts. Then put the relevant IRQ input back to high level within the interrupt handling routine and
clear the IRQnF bit (n = 7 to 0) in ISR to 0. If the relevant IRQ input is put back to high level
before the interrupt handling starts, the relevant interrupt may not be executed.
The detection of IRQ7 to IRQ0 interrupts does not depend on whether the relevant pin has been
set for input or output. Therefore, when a pin is used as an external interrupt input pin, clear the
DDR bit of the corresponding port to 0 so it is not used as an I/O pin for another function.
A block diagram of interrupts IRQ15 to IRQ0 is shown in figure 5.2.
independent vector address.
edge, rising edge, or both edges, at pins IRQ7 to IRQ0.
by software.
NMI Interrupt
IRQ7 to IRQ0 Interrupts
Interrupt Sources
External Interrupt Sources
Rev. 1.00 Sep. 21, 2006 Page 83 of 658
Section 5 Interrupt Controller
REJ09B0310-0100
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