p2125vps20 Renesas Electronics Corporation., p2125vps20 Datasheet - Page 467

• Manufacturer Part Number: p2125vps20
• Description: 16-bit Single-chip Microcomputer H8s Family / H8s/2100 Series
• Manufacturer: Renesas Electronics Corporation.

Notes: 1. Does not meet the I
7. Notes on ICDR read at end of master reception
Clearing of the MST bit after completion of master transmission/reception, or other modifications
of IIC control bits to change the transmit/receive operating mode or settings, must be carried out
during interval (a) in figure 16.29 (after confirming that the BBSY bit in ICCR has been cleared to
0).
Item
t
SDAHO
To halt reception at the end of a receive operation in master receive mode, set the TRS bit to 1
and write 0 to BBSY and SCP in ICCR. This changes SDA from low to high when SCL is
high, and generates the stop condition. After this, receive data can be read by means of an
ICDR read, but if data remains in the buffer the ICDRS receive data will not be transferred to
ICDR (ICDRR), and so it will not be possible to read the second byte of data.
If it is necessary to read the second byte of data, issue the stop condition in master receive
mode (i.e. with the TRS bit cleared to 0). When reading the receive data, first confirm that the
BBSY bit in ICCR is cleared to 0, the stop condition has been generated, and the bus has been
released, then read ICDR with TRS cleared to 0.
Note that if the receive data (ICDR data) is read in the interval between execution of the
instruction for issuance of the stop condition (writing of 0 to BBSY and SCP in ICCR) and the
actual generation of the stop condition, the clock may not be output correctly in subsequent
master transmission.
2. Value when the IICX bit is set to 1. When the IICX bit is cleared to 0, the value is
3. Calculated using the I
t
Indication
3 t
cyc
cyc
is necessary: (a) secure a start/stop condition issuance interval; (b) adjust the rise and
fall times by means of a pull-up resistor and capacitive load; (c) reduce the transfer rate;
(d) select slave devices whose input timing permits this output timing.
The values in the above table will vary depending on the settings of the IICX bit and bits
CKS0 to CKS2. Depending on the frequency it may not be possible to achieve the
maximum transfer rate; therefore, whether or not the I
met must be determined in accordance with the actual setting conditions.
(t
speed mode: 1300 ns min.).
SCLL
– 6 t
cyc
Standard mode
High-speed
mode
).
2
C bus interface specification. Remedial action such as the following
2
C bus specification values (standard mode: 4700 ns min.; high-
t
Influence
(Max.)
0
0
Sr
/t
Sf
Time Indication (at Maximum Transfer Rate) [ns]
I
Specifi-
cation
(Min.)
0
0
2
C Bus
φ =
8 MHz
375
375
Rev. 1.00 Sep. 21, 2006 Page 429 of 658
2
C bus interface specifications are
300
300
Section 16 I
φ =
10 MHz
188
188
φ =
16 MHz
2
C Bus Interface (IIC)
REJ09B0310-0100
150
150
φ =
20 MHz