p2125vps20 Renesas Electronics Corporation., p2125vps20 Datasheet - Page 269
p2125vps20
Manufacturer Part Number
p2125vps20
Description
16-bit Single-chip Microcomputer H8s Family / H8s/2100 Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.P2125VPS20.pdf
(700 pages)
- Current page: 269 of 700
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11.5.5
ICRC and ICRD can operate as buffers for ICRA and ICRB, respectively. Figure 11.9 shows how
input capture operates when ICRC is used as ICRA's buffer register (BUFEA = 1) and IEDGA and
IEDGC are set to different values (IEDGA = 0 and IEDGC = 1, or IEDGA = 1 and IEDGC = 0),
so that input capture is performed on both the rising and falling edges of FTIA.
Even when ICRC or ICRD is used as a buffer register, its input capture flag is set by the selected
transition of its input capture signal. For example, if ICRC is used to buffer ICRA, when the edge
transition selected by the IEDGC bit occurs on the FTIC input capture line, ICFC will be set, and
if the ICICE bit is set at this time, an interrupt will be requested. The FRC value will not be
transferred to ICRC, however. In buffered input capture, if either set of two registers to which data
will be transferred (ICRA and ICRC, or ICRB and ICRD) is being read when the input capture
input signal arrives, input capture is delayed by one system clock (φ). Figure 11.10 shows the
timing when BUFEA = 1.
φ
FTIA
Input capture
signal
FRC
ICRA
ICRC
Buffered Input Capture Input Timing
M
m
Figure 11.9 Buffered Input Capture Timing
n
M
n
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Section 11 16-Bit Free-Running Timer (FRT)
Rev. 1.00 Sep. 21, 2006 Page 231 of 658
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M
n
N
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REJ09B0310-0100
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