p2125vps20 Renesas Electronics Corporation., p2125vps20 Datasheet - Page 29

• Manufacturer Part Number: p2125vps20
• Description: 16-bit Single-chip Microcomputer H8s Family / H8s/2100 Series
• Manufacturer: Renesas Electronics Corporation.

Figure 16.30 Flowchart for Start Condition Issuance Instruction
for Retransmission and Timing ............................................................................. 431
Figure 16.31 Stop Condition Issuance Timing ........................................................................... 432
Figure 16.32 IRIC Flag Clearing Timing When WAIT = 1 ....................................................... 433
Figure 16.33 ICDR Read and ICCR Access Timing in Slave Transmit Mode........................... 434
Figure 16.34 TRS Bit Set Timing in Slave Mode....................................................................... 435
Figure 16.35 Diagram of Erroneous Operation when Arbitration is Lost................................... 436
Figure 16.36 IRIC Flag Clear Timing in Wait Operation........................................................... 437
Section 17 A/D Converter
Figure 17.1 Block Diagram of A/D Converter ........................................................................... 440
Figure 17.2 A/D Conversion Timing .......................................................................................... 447
Figure 17.3 External Trigger Input Timing ................................................................................ 448
Figure 17.4 A/D Conversion Accuracy Definitions.................................................................... 450
Figure 17.5 A/D Conversion Accuracy Definitions.................................................................... 450
Figure 17.6 Example of Analog Input Circuit ............................................................................ 451
Figure 17.7 Example of Analog Input Protection Circuit ........................................................... 453
Figure 17.8 Analog Input Pin Equivalent Circuit ....................................................................... 453
Section 19 Flash Memory (0.18-µm F-ZTAT Version)
Figure 19.1 Block Diagram of Flash Memory............................................................................ 458
Figure 19.2 Mode Transition for Flash Memory ........................................................................ 459
Figure 19.3 Flash Memory Configuration .................................................................................. 461
Figure 19.4 Block Division of User MAT (1) ............................................................................ 462
Figure 19.4 Block Division of User MAT (2) ............................................................................ 463
Figure 19.5 Overview of User Procedure Program..................................................................... 464
Figure 19.6 System Configuration in Boot Mode....................................................................... 487
Figure 19.7 Automatic-Bit-Rate Adjustment Operation of SCI ................................................. 487
Figure 19.8 Overview of Boot Mode State Transition Diagram................................................. 489
Figure 19.9 Programming/Erasing Overview Flow.................................................................... 490
Figure 19.10 RAM Map when Programming/Erasing is Executed ............................................ 491
Figure 19.11 Programming Procedure........................................................................................ 492
Figure 19.12 Erasing Procedure.................................................................................................. 498
Figure 19.13 Repeating Procedure of Erasing and Programming............................................... 500
Figure 19.14 Procedure for Programming User MAT in User Boot Mode ................................ 502
Figure 19.15 Procedure for Erasing User MAT in User Boot Mode .......................................... 504
Figure 19.16 Transitions to Error-Protection State..................................................................... 516
Figure 19.17 Switching between User MAT and User Boot MAT ............................................ 517
Figure 19.18 Memory Map in Programmer Mode...................................................................... 518
Figure 19.19 Boot Program States .............................................................................................. 520
Figure 19.20 Bit-Rate-Adjustment Sequence ............................................................................. 521
Rev. 1.00 Sep. 21, 2006 Page xxix of xxxviii