p2125vps20 Renesas Electronics Corporation., p2125vps20 Datasheet - Page 392

• Manufacturer Part Number: p2125vps20
• Description: 16-bit Single-chip Microcomputer H8s Family / H8s/2100 Series
• Manufacturer: Renesas Electronics Corporation.

Section 15 Serial Communication Interface (SCI)
Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the ORER,
FER, PER, and RDRF bits to 0 before resuming reception. Figure 15.19 shows a sample flowchart
for serial data reception.
Rev. 1.00 Sep. 21, 2006 Page 354 of 658
REJ09B0310-0100
[3]
No
No
Read receive data in RDR and
Clear ORER flag in SSR to 0
clear RDRF flag in SSR to 0
Overrun error processing
Read ORER flag in SSR
Read RDRF flag in SSR
Clear RE bit in SCR to 0
All data received?
End of reception
Error processing
Start reception
Initialization
Figure 15.19 Sample Serial Reception Flowchart
ORER = 1
RDRF = 1
End
Yes
Yes
No
(Continued below)
Error processing
Yes
[1]
[2]
[3]
[4]
[5]
[6]
[1]
[2]
[4]
[5]
Note: The SMR, SCR, SCMR, and BRR
Serial reception continuation procedure:
SCI initialization:
The RxD pin is automatically designated as
the receive data input pin.
[3] Receive error processing:
If a receive error occurs, read the ORER
flag in SSR, and after performing the
appropriate error processing, clear the
ORER flag to 0. Transfer cannot be
resumed if the ORER flag is set to 1.
SCI status check and receive data read:
Read SSR and check that the RDRF flag is
set to 1, then read the receive data in RDR
and clear the RDRF flag to 0.
Transition of the RDRF flag from 0 to 1 can
also be identified by an RXI interrupt.
To continue serial reception, before the
MSB (bit 7) of the current frame is received,
reading the RDRF flag, reading RDR, and
clearing the RDRF flag to 0 should be
finished.
However, the RDRF flag is cleared
automatically when the DTC is initiated by a
receive data full interrupt (RXI) and reads
data from RDR.
registers should not be written to
during the period from the start to the
end of reception. This does not apply
to the processing at step [6].