p2125vps20 Renesas Electronics Corporation., p2125vps20 Datasheet - Page 394

• Manufacturer Part Number: p2125vps20
• Description: 16-bit Single-chip Microcomputer H8s Family / H8s/2100 Series
• Manufacturer: Renesas Electronics Corporation.

Section 15 Serial Communication Interface (SCI)
Rev. 1.00 Sep. 21, 2006 Page 356 of 658
REJ09B0310-0100
Note: When switching from transmit or receive operation to simultaneous
Figure 15.20 Sample Flowchart of Simultaneous Serial Transmission and Reception
The SMR, SCR, SCMR, and BRR registers should not be written to
during the period from the start to the end of transmission/reception.
This does not apply to the processing at step [6].
transmit and receive operations, first clear the TE bit and RE bit to 0,
then set both these bits to 1 simultaneously.
No
No
No
Clear TE and RE bits in SCR to 0
Read receive data in RDR, and
Write transmit data to TDR and
End of transmission/reception
Start transmission/reception
clear TDRE flag in SSR to 0
clear RDRF flag in SSR to 0
Read ORER flag in SSR
Read TDRE flag in SSR
Read RDRF flag in SSR
All data received?
Initialization
ORER = 1
TDRE = 1
RDRF = 1
Yes
Yes
Yes
No
Error processing
Yes
[1]
[2]
[4]
[5]
[6]
[3]
[1]
[2]
[3]
[4]
[5]
Serial transmission/reception
SCI initialization:
The TxD pin is designated as the
transmit data output pin, and the RxD pin
is designated as the receive data input
pin, enabling simultaneous transmit and
receive operations.
SCI status check and transmit data write:
Read SSR and check that the TDRE flag
is set to 1, then write transmit data to
TDR and clear the TDRE flag to 0.
Transition of the TDRE flag from 0 to 1
can also be identified by a TXI interrupt.
Receive error processing:
If a receive error occurs, read the ORER
flag in SSR, and after performing the
appropriate error processing, clear the
ORER flag to 0. Transmission/reception
cannot be resumed if the ORER flag is
set to 1.
SCI status check and receive data read:
Read SSR and check that the RDRF flag
is set to 1, then read the receive data in
RDR and clear the RDRF flag to 0.
Transition of the RDRF flag from 0 to 1
can also be identified by an RXI
interrupt.
continuation procedure:
To continue serial transmission/
reception, before the MSB (bit 7) of the
current frame is received, finish reading
the RDRF flag, reading RDR, and
clearing the RDRF flag to 0. Also, before
the MSB (bit 7) of the current frame is
transmitted, read 1 from the TDRE flag
to confirm that writing is possible. Then
write data to TDR and clear the TDRE
flag to 0.
However, the TDRE flag is checked and
cleared automatically when the DTC is
initiated by a transmit data empty
interrupt (TXI) request and writes data to
TDR. Similarly, the RDRF flag is cleared
automatically when the DTC is initiated
by a receive data full interrupt (RXI) and
reads data from RDR.