p2125vps20 Renesas Electronics Corporation., p2125vps20 Datasheet - Page 137
p2125vps20
Manufacturer Part Number
p2125vps20
Description
16-bit Single-chip Microcomputer H8s Family / H8s/2100 Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.P2125VPS20.pdf
(700 pages)
- Current page: 137 of 700
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The interrupt controller has three main functions in DTC control.
(1)
It is possible to select a DTC activation request or CPU interrupt request for an interrupt source
with the DTCE bit in DTCERA to DTCERE of the DTC. After a DTC data transfer, the DTCE bit
can be cleared to 0 and an interrupt request sent to the CPU in accordance with the specification of
the DISEL bit in MRB of the DTC. When the DTC performs the specified number of data
transfers and the transfer counter reaches 0, following the DTC data transfer the DTCE bit is
cleared to 0 and an interrupt request is sent to the CPU.
(2)
The DTC activation source is selected in accordance with the default priority order, and is not
affected by mask or priority levels. See section 7.4, Location of Register Information and DTC
Vector Table, for the respective priorities.
(3)
If the same interrupt is selected as a DTC activation source and a CPU interrupt source, the DTC
data transfer is performed first, followed by CPU interrupt exception handling.
Table 5.9 summarizes interrupt source selection and interrupt source clearance control according
to the settings of the DTCE bit in DTCERA to DTCERE of the DTC and the DISEL bit in MRB
of the DTC.
Table 5.9
[Legend]
∆:
×:
*:
DTCE
0
1
:
Selection of Interrupt Source
Determination of Priority
Operation Order
The relevant interrupt is used. Interrupt source clearing is performed.
(The CPU should clear the source flag in the interrupt handling routine.)
The relevant interrupt is used. The interrupt source is not cleared.
The relevant interrupt cannot be used.
Don't care
Interrupt Source Selection and Clearing Control
Settings
DTC
DISEL
*
0
1
DTC
×
∆
Interrupt Source Selection/Clearing Control
Rev. 1.00 Sep. 21, 2006 Page 99 of 658
Section 5 Interrupt Controller
CPU
∆
×
∆
REJ09B0310-0100
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