p2125vps20 Renesas Electronics Corporation., p2125vps20 Datasheet - Page 464

• Manufacturer Part Number: p2125vps20
• Description: 16-bit Single-chip Microcomputer H8s Family / H8s/2100 Series
• Manufacturer: Renesas Electronics Corporation.

Section 16 I
Table 16.9 I
Note:
4. SCL and SDA inputs are sampled in synchronization with the internal clock. The AC timing
5. The I
Rev. 1.00 Sep. 21, 2006 Page 426 of 658
REJ09B0310-0100
Item
SCL output cycle time
SCL output high pulse width
SCL output low pulse width
SDA output bus free time
Start condition output hold time
Retransmission start condition output
setup time
Stop condition output setup time
Data output setup time (master)
Data output setup time (slave)
Data output hold time
therefore depends on the system clock cycle tcyc, as shown in section 24, Electrical
Characteristics. Note that the I
system clock frequency of less than 5 MHz.
speed mode). In master mode, the I
one bit at a time during communication. If tsr (the time for SCL to go from low to VIH)
exceeds the time determined by the input clock of the I
is extended. The SCL rise time is determined by the pull-up resistance and load capacitance of
the SCL line. To insure proper operation at the set transfer rate, adjust the pull-up resistance
and load capacitance so that the SCL rise time does not exceed the values given in table 16.10.
*
2
C bus interface specification for the SCL rise time tsr is 1000 ns or less (300 ns for high-
6t
2
C Bus Interface (IIC)
cyc
2
C Bus Timing (SCL and SDA Outputs)
when IICX is 0, 12t
2
cyc
C bus interface AC timing specifications will not be met with a
when 1.
2
C bus interface monitors the SCL line and synchronizes
Symbol
t
t
t
t
t
t
t
t
t
SCLO
SCLHO
SCLLO
BUFO
STAHO
STASO
STOSO
SDASO
SDAHO
Output Timing
28t
0.5t
0.5t
0.5t
0.5t
1t
0.5t
1t
1t
3t
SCLO
SCLLO
SCLL
cyc
cyc
SCLO
SCLO
SCLO
SCLO
SCLO
– (6t
to 256t
2
– 3t
C bus interface, the high period of SCL
– 1t
– 1t
+ 2t
cyc
cyc
cyc
cyc
cyc
or 12t
cyc
cyc
*)
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
See figure
24.26.