p2125vps20 Renesas Electronics Corporation., p2125vps20 Datasheet - Page 614

• Manufacturer Part Number: p2125vps20
• Description: 16-bit Single-chip Microcomputer H8s Family / H8s/2100 Series
• Manufacturer: Renesas Electronics Corporation.

Section 22 Power-Down Modes
22.5
Software Standby Mode
The CPU makes a transition to software standby mode when the SLEEP instruction is executed
with the SSBY bit in SBYCR set to 1, the LSON bit in LPWRCR cleared to 0, and the PSS bit in
TCSR (WDT_1) cleared to 0. In software standby mode, the CPU, on-chip peripheral modules,
and clock pulse generator all stop. However, the contents of the CPU registers, on-chip RAM data,
I/O ports, and the states of on-chip peripheral modules other than the SCI, PWM, PWMX, and
A/D converter are retained as long as the prescribed voltage is supplied.
Software standby mode is cleared by an external interrupt (NMI, IRQ0 to IRQ7), RES pin input,
or STBY pin input.
When an external interrupt request signal is input, system clock oscillation starts, and after the
elapse of the time set in bits STS2 to STS0 in SBYCR, software standby mode is cleared, and
interrupt exception handling is started. When clearing software standby mode with an IRQ0 to
IRQ7 interrupt, set the corresponding enable bit to 1. In the case of an IRQ0 to IRQ7 interrupt,
software standby mode is not cleared if the corresponding enable bit is cleared to 0 or if the
interrupt has been masked by the CPU.
When the RES pin is driven low, the clock pulse generator starts oscillation. Simultaneously with
the start of system clock oscillation, the system clock is supplied to the entire LSI. Note that the
RES pin must be held low until clock oscillation is stabilized. If the RES pin is driven high after
the clock oscillation stabilization time has elapsed, the CPU starts reset exception handling.
When the STBY pin is driven low, software standby mode is cleared and a transition is made to
hardware standby mode.
Rev. 1.00 Sep. 21, 2006 Page 576 of 658
REJ09B0310-0100