p2125vps20 Renesas Electronics Corporation., p2125vps20 Datasheet - Page 472

• Manufacturer Part Number: p2125vps20
• Description: 16-bit Single-chip Microcomputer H8s Family / H8s/2100 Series
• Manufacturer: Renesas Electronics Corporation.

Section 16 I
Note: This restriction on usage can be canceled by setting the FNC1 and FNC0 bits to B'11 in
12. Note on TRS bit setting in slave mode
Rev. 1.00 Sep. 21, 2006 Page 434 of 658
REJ09B0310-0100
In I
edge of the 9th clock pulse or the stop condition before detecting the next rising edge on the
SCL pin (the time indicated as (a) in figure 16.34), the bit value becomes valid immediately
when it is set. However, if the TRS bit is set during the other time (the time indicated as (b) in
figure 16.34), the bit value is suspended and remains invalid until the rising edge of the 9th
clock pulse or the stop condition is detected. Therefore, when the address is received after the
restart condition is input without the stop condition, the effective TRS bit value remains 1
(transmit mode) internally and thus the acknowledge bit is not transmitted after the address has
been received at the 9th clock pulse.
To receive the address in slave mode, clear the TRS bit to 0 during the time indicated as (a) in
figure 16.34. To release the SCL low level that is held by means of the wait function in slave
mode, clear the TRS bit to and then dummy-read ICDR.
2
C bus interface slave mode, if the TRS bit value in ICCR is set after detecting the rising
ICXR.
Figure 16.33 ICDR Read and ICCR Access Timing in Slave Transmit Mode
SDA
SCL
TRS bit
2
C Bus Interface (IIC)
Address reception
R/W
8
The rise of the 9th clock is detected
A
9
ICDR read and ICCR read/write are disabled
Waveform at problem
occurrence
(6 system clock period)
ICDR write
Data transmission
Bit 7