p2125vps20 Renesas Electronics Corporation., p2125vps20 Datasheet - Page 151

• Manufacturer Part Number: p2125vps20
• Description: 16-bit Single-chip Microcomputer H8s Family / H8s/2100 Series
• Manufacturer: Renesas Electronics Corporation.

6.5
The basic bus interface enables direct connection to ROM and SRAM. For details on selection of
the bus specifications when using the basic bus interface, see table 6.2.
6.5.1
Data sizes for the CPU and other internal bus masters are byte, word, and longword. The BSC has
a data alignment function, and controls whether the upper data bus (D15 to D8) or lower data bus
(D7 to D0) is used when the external address space is accessed, according to the bus specifications
for the area being accessed (8-bit access space or 16-bit access space) and the data size. This LSI
has only the upper data bus and only data alignment for the 8-bit access space is applied. The pins
for the upper data bus in this LSI are D7 to D0.
(1)
Figure 6.3 illustrates data alignment control for the 8-bit access space. With the 8-bit access space,
the upper data bus (D15 to D8) is always used for accesses. The amount of data that can be
accessed at one time is one byte: a word access is performed as two byte accesses, and a longword
access, as four byte accesses.
8-Bit Access Space
Basic Bus Interface
Data Size and Data Alignment
Figure 6.3 Access Sizes and Data Alignment Control (8-Bit Access Space)
Byte size
Word size
Longword
size
1st bus cycle
2nd bus cycle
1st bus cycle
2nd bus cycle
3rd bus cycle
4th bus cycle
D15
Upper data bus
Rev. 1.00 Sep. 21, 2006 Page 113 of 658
D8 D7
Lower data bus
Section 6 Bus Controller (BSC)
D0
REJ09B0310-0100