p2125vps20 Renesas Electronics Corporation., p2125vps20 Datasheet - Page 262

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p2125vps20

Manufacturer Part Number
p2125vps20
Description
16-bit Single-chip Microcomputer H8s Family / H8s/2100 Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
Section 11 16-Bit Free-Running Timer (FRT)
11.3.8
TCR selects the rising or falling edge of the input capture signals, enables the input capture buffer
mode, and selects the FRC clock source.
Rev. 1.00 Sep. 21, 2006 Page 224 of 658
REJ09B0310-0100
Bit
7
6
5
4
3
2
Bit Name
IEDGA
IEDGB
IEDGC
IEDGD
BUFEA
BUFEB
Timer Control Register (TCR)
0
0
0
0
0
0
Initial
Value
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Input Edge Select A
Selects the rising or falling edge of the input capture A
signal (FTIA).
0: Capture on the falling edge of FTIA
1: Capture on the rising edge of FTIA
Input Edge Select B
Selects the rising or falling edge of the input capture B
signal (FTIB).
0: Capture on the falling edge of FTIB
1: Capture on the rising edge of FTIB
Input Edge Select C
Selects the rising or falling edge of the input capture C
signal (FTIC).
0: Capture on the falling edge of FTIC
1: Capture on the rising edge of FTIC
Input Edge Select D
Selects the rising or falling edge of the input capture D
signal (FTID).
0: Capture on the falling edge of FTID
1: Capture on the rising edge of FTID
Buffer Enable A
Selects whether ICRC is to be used as a buffer register for
ICRA.
0: ICRC is not used as a buffer register for ICRA
1: ICRC is used as a buffer register for ICRA
Buffer Enable B
Selects whether ICRD is to be used as a buffer register for
ICRB.
0: ICRD is not used as a buffer register for ICRB
1: ICRD is used as a buffer register for ICRB

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