p2125vps20 Renesas Electronics Corporation., p2125vps20 Datasheet - Page 463

• Manufacturer Part Number: p2125vps20
• Description: 16-bit Single-chip Microcomputer H8s Family / H8s/2100 Series
• Manufacturer: Renesas Electronics Corporation.

16.5
The IIC has interrupt sources, IICI0 and IICI1. Table 16.8 shows the interrupt sources and priority.
Individual interrupt sources can be enabled or disabled using the enable bit in ICCR, and are sent
to the interrupt controller independently.
An IICI interrupt can activate the DTC to allow data transfer.
Table 16.8 IIC Interrupt Sources
16.6
1. In master mode, if an instruction to generate a start condition is issued and then an instruction
Note: * An illegal procedure in the I
2. Either of the following two conditions will start the next transfer. Pay attention to these
3. Table 16.9 shows the timing of SCL and SDA outputs in synchronization with the internal
Channel
0
1
to generate a stop condition is issued before the start condition is output to the I
condition will be output correctly. To output the stop condition followed by the start
condition*, after issuing the instruction that generates the start condition, read DR in each I
bus output pin, and check that SCL and SDA are both low. The pin states can be monitored by
reading DR even if the ICE bit is set to 1. Then issue the instruction that generates the stop
condition. Note that SCL may not yet have gone low when BBSY is cleared to 0.
conditions when accessing to ICDR.
 Write to ICDR when ICE = 1 and TRS = 1 (including automatic transfer from ICDRT to
 Read from ICDR when ICE = 1 and TRS = 0 (including automatic transfer from ICDRS to
clock. Timings on the bus are determined by the rise and fall times of signals affected by the
bus load capacitance, series resistance, and parallel resistance.
ICDRS)
ICDRR)
Interrupt Sources
Usage Notes
Name
IICI0
IICI1
Enable
Bit
IEIC
IEIC
Interrupt Source
I
interrupt request
I
interrupt request
2
2
C bus interface
C bus interface
2
C bus specification.
Interrupt
Flag
IRIC
IRIC
Rev. 1.00 Sep. 21, 2006 Page 425 of 658
Section 16 I
DTC Activation
Possible
Possible
2
C Bus Interface (IIC)
REJ09B0310-0100
2
C bus, neither
High
Priority
Low
2
C