PEB2256E INFINEON [Infineon Technologies AG], PEB2256E Datasheet - Page 103

• Manufacturer Part Number: PEB2256E
• Description: E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications
• Manufacturer: INFINEON [Infineon Technologies AG]

FALC56 V1.2
PEB 2256
Functional Description E1
2.048 MHz cycle and is clocked off with the rising or falling edge of the clock which is in/
output on port SCLKR (see SIC3.RESR/X).
Compared to the receive path the inverse functions are performed for the transmit
direction.
The interface to the transmit system highway is realized by two data buses, one for the
data XDI and one for the signaling data XSIG. The time slot assignment is equivalent to
the receive direction.
Latching of data is controlled by the system clock (SCLKX) and the synchronization
pulse (SYPX/XMFS) in combination with the programmed offset values for the transmit
time slot/clock slot counters XC1/0. The frequency of the working clock of 2.048/4.096/
8.192/16.384 MHz for the transmit system interface is programmable by SIC1.SSC1/0.
Refer also
toTable
23.
The received bit stream on ports XDI and XSIG can be multiplexed internally on a time
slot basis, if enabled by SIC3.TTRF = 1. The data received on port XSIG can be sampled
if the transmit signaling marker XSIGM is active high. Data on port XDI is sampled if
XSIGM is low for the corresponding time slot. Programming the XSIGM marker is done
with registers TTR(4:1).
Data Sheet
103
2002-08-27