PEB2256E INFINEON [Infineon Technologies AG], PEB2256E Datasheet - Page 71

• Manufacturer Part Number: PEB2256E
• Description: E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications
• Manufacturer: INFINEON [Infineon Technologies AG]

• Frame alignment between system frame and receive route frame
• Reporting and controlling of slips
Controlled by special signals generated by the receiver, the unipolar bit stream is
converted into bit-parallel data which is circularly written to the elastic buffer using
internally generated receive route clock (RCLK).
Reading of stored data is controlled by the system clock sourced by SCLKR or by the
receive jitter attenuator and the synchronization pulse (SYPR) together with the
programmed offset values for the receive time slot/clock slot counters. After conversion
into a serial data stream, the data is given out on port RDO. If the receive buffer is
bypassed programming of the time slot offset is disabled and data is clocked off with
RCLK instead of SCLKR.
In one frame or short buffer mode the delay through the receive buffer is reduced to an
average delay of 128 or 46 bits. In bypass mode the time slot assigner is disabled. In this
case SYPR programmed as input is ignored. Slips are performed in all buffer modes
except the bypass mode. After a slip is detected the read pointer is adjusted to one half
of the current buffer size.
The following table gives an overview of the receive buffer operating mode.
I
Table 15
Buffer Size
(SIC1.RBS1/0)
bypass
short buffer
1 frame
2 frames
1)
In single frame mode (SIC1.RBS), values of receive time slot offset (RC1/0) have to be
specified great enough to prevent too great approach of frame begin of line side and
frame begin of system side.
Figure 19
A slip condition is detected when the write pointer (W) and the read pointer (R) of the
memory are nearly coincident, i.e. the read pointer is within the slip limits (S +, S –). If a
Data Sheet
In bypass mode the clock provided on pin SCLKR is ignored. Clocking is done with RCLK.
1)
gives an idea of operation of the receive elastic buffer:
Receive Buffer Operating Modes (E1)
TS Offset programming
(RC1/0) + SYPR = input
disabled
recommended:
SYPR = output
not recommended,
recommended:
SYPR = output
not recommended,
recommended:
SYPR = output
enabled
71
Slip performance
no
yes
yes
yes
Functional Description E1
FALC56 V1.2
PEB 2256
2002-08-27