PEB2256E INFINEON [Infineon Technologies AG], PEB2256E Datasheet - Page 197

• Manufacturer Part Number: PEB2256E
• Description: E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications
• Manufacturer: INFINEON [Infineon Technologies AG]

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Table 53
Basic Set Up
Master clocking mode
T1/J1 mode select
Specification of line
interface and clock
generation
Line interface coding
Loss-of-signal detection/
recovery conditions
System clocking and data
rate
Channel translation mode
Transmit offset counters
Receive offset counters
AIS to system interface
Operational Set Up
Select framing
Framing additions
Synchronization mode
Signaling mode
Note: Read access to unused register addresses: value should be ignored.
Data Sheet
Write access to unused register addresses: should be avoided, or set to “00”hex.
All control registers (except XFIFO, XS(12:1), CMDR, DEC) are of type read/write
Initialization Parameters (T1/J1)
T1
GCM(6:1) according to external MCLK clock frequency
FMR1.PMOD = 1,
RC0.SJR = 0
LIM0, LIM1, XPM(2:0)
FMR0.XC(1:0), FMR0.RC(1:0)
PCD, PCR, LIM1, LIM2
SIC1.SSC(1:0), SIC1.SSD1, FMR1.SSD0, CMR1.IRSP/
IRSC/IXSP/IXSC
FMR1.CTM
XC0.XCO, XC1.XTO
RC0.RCO, RC1.RTO
FMR2.DAIS/SAIS
FMR4.FM(1:0)
FMR1.CRC, FMR0.SRAF
FMR4.AUTO, FMR4.SSC(1:0), FMR2.MCSP,
FMR2.SSP
FMR5.EIBR, XC0.BRM, MODE, MODE2, MODE3,
CCR1, CCR2, RAH(2:1), RAL(2:1)
197
Operational Description T1/J1
J1
FMR1.PMOD = 1,
RC0.SJR = 1
FALC56 V1.2
PEB 2256
2002-08-27