PEB2256E INFINEON [Infineon Technologies AG], PEB2256E Datasheet - Page 165

• Manufacturer Part Number: PEB2256E
• Description: E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications
• Manufacturer: INFINEON [Infineon Technologies AG]

5.5
The FALC56 offers a flexible feature for system designers where for transmit and receive
direction different system clocks and system pulses are necessary. The interface to the
receive system highway is realized by two data buses, one for the data RDO and one for
the signaling data RSIG. The receive highway is clocked on pin SCLKR, while the
interface to the transmit system highway is independently clocked on pin SCLKX. The
frequency of these working clocks and the data rate of 2.048/4.096/8.192/16.384/1.544/
3.088/6.192/12.352 Mbit/s for the receive and transmit system interface is
programmable by SIC1.SSC1/0, SIC2.SSC2 and SIC1.SSD1, FMR1.SSD0. Selectable
system clock and data rates and their valid combinations are shown in the table below.
Table 44
System Data Rate
1.544/2.048 Mbit/s
3.088/4.096 Mbit/s
6.176/8.192 Mbit/s
12.352/16.384 Mbit/s
x = valid, -- = invalid
Generally the data or marker on the system interface are clocked off or latched on the
rising or falling edge (SIC3.RESR/X) of the SCLKR/X clock. Some clocking rates allow
transmission of time slots in different channel phases. Each channel phase which shall
be active on ports RDO, XDI, RP(A:D) and XP(A:D) is programmable by bit
SIC2.SICS(2:0), the remaining channel phases are cleared or ignored.
The signals on pin SYPR in combination with the assigned time slot offset in register RC0
and RC1 define the beginning of a frame on the receive system highway. The signal on
pin SYPX or XMFS together with the assigned time slot offset in register XC0 and XC1
define the beginning of a frame on the transmit system highway.
Adjusting the frame begin (time slot 0, bit 0) relative to SYPR/X or XMFS is possible in
the range of 0 to 125 µs. The minimum shift of varying the time slot 0 begin can be
programmed between 1 bit and 1/8 bit depending of the system clocking and data rate,
e.g. with a clocking/data rate of 2.048 MHz shifting is done bit by bit, while running the
FALC56 with 16.384 MHz and 2.048 Mbit/s data rate it is done by 1/8 bit.
A receive frame marker RFM can be activated during any bit position of the entire frame.
Programming is done with registers RC1/0. The pin function RFM is selected by
PC(4:1).RPC(2:0) = 001. The RFM selection disables the internal time slot assigner, no
offset programming is performed. The receive frame marker is active high for one 1.544/
Data Sheet
System Interface in T1/J1 Mode
System Clocking and Data Rates (T1/J1)
Clock Rate
1.544/2.048
MHz
x
--
--
--
Clock Rate
3.088/4.096
MHz
x
x
--
--
165
Functional Description T1/J1
Clock Rate
6.176/8.192
MHz
x
x
x
--
FALC56 V1.2
Clock Rate
12.352/
16.384 MHz
x
x
x
x
PEB 2256
2002-08-27