PEB2256E INFINEON [Infineon Technologies AG], PEB2256E Datasheet - Page 224

• Manufacturer Part Number: PEB2256E
• Description: E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications
• Manufacturer: INFINEON [Infineon Technologies AG]

Common Configuration Register 2 (Read/Write)
Value after reset: 00
CCR2
Note: Unused bits have to be cleared.
RADD
RCRC
XCRC
Data Sheet
7
Receive Address Pushed to RFIFO - HDLC Channel 1
If this bit is set, the received HDLC address information (1 or 2 bytes,
depending on the address mode selected by MODE.MDS0) is pushed
to RFIFO. This function is applicable in non-auto mode and
transparent mode 1.
RADD must be set, if SS7 mode is selected.
Receive CRC on/off - HDLC Channel 1
Only applicable in non-auto mode.
If this bit is set, the received CRC checksum is written to RFIFO
(CRC-ITU-T: 2 bytes). The checksum, consisting of the 2 last bytes in
the received frame, is followed by the status information byte
(contents of register RSIS). The received CRC checksum is
additionally checked for correctness. If non-auto mode is selected,
the limits for “valid frame” check are modified (refer to RSIS.VFR).
Transmit CRC on/off - HDLC Channel 1
If this bit is set, the CRC checksum is not generated internally. It has
to be written to the transmit FIFO as the last two bytes. The
transmitted frame is closed automatically with a closing flag.
Note: The FALC56 does not check whether the length of the frame,
H
i.e. the number of bytes to be transmitted makes sense or not.
RADD
224
RCRC
XCRC
FALC56 V1.2
E1 Registers
0
PEB 2256
2002-08-27
(0A)