PEB2256E INFINEON [Infineon Technologies AG], PEB2256E Datasheet - Page 434

• Manufacturer Part Number: PEB2256E
• Description: E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications
• Manufacturer: INFINEON [Infineon Technologies AG]

RSN
RSP
Interrupt Status Register 4 (Read)
ISR4
All bits are reset when ISR4 is read.
If bit GCR.VIS is set, interrupt statuses in ISR4 are flagged although they are masked by
register IMR4. However, these masked interrupt statuses neither generate a signal on
INT, nor are visible in register GIS.
XSP
XSN
RME2
Data Sheet
XSP
7
Receive Slip Negative
The frequency of the receive route clock is greater than the frequency
of the receive system interface working clock based on 1.544 MHz. A
frame is skipped. It is set during alarm simulation.
Receive Slip Positive
The frequency of the receive route clock is less than the frequency of
the receive system interface working clock based on 1.544 MHz. A
frame is repeated. It is set during alarm simulation.
Transmit Slip Positive
The frequency of the transmit clock is less than the frequency of the
transmit system interface working clock based on 1.544 MHz. A frame
is repeated. After a slip has performed writing of register XC1 is not
necessary.
Transmit Slip Negative
The frequency of the transmit clock is greater than the frequency of
the transmit system interface working clock based on 1.544 MHz. A
frame is skipped. After a slip has performed writing of register XC1 is
not necessary.
Receive Message End - HDLC Channel 2
One complete message of length less than 32 bytes, or the last part
of a frame at least 32 bytes long is stored in the receive FIFO2,
including the status byte.
The complete message length can be determined reading register
RBC2, the number of bytes currently stored in RFIFO2 is given by
RBC2(6:0). Additional information is available in register RSIS2.
XSN
RME2
RFS2
434
RDO2
ALLS2
XDU2
T1/J1 Registers
RPF2
FALC56 V1.2
0
PEB 2256
2002-08-27
(6C)