PEB2256E INFINEON [Infineon Technologies AG], PEB2256E Datasheet - Page 389

• Manufacturer Part Number: PEB2256E
• Description: E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications
• Manufacturer: INFINEON [Infineon Technologies AG]

Command Register 2 (Write)
Value after reset: 00
CMDR2
RSUC
XPPR
Command Register 3 (Write)
Value after reset: 00
CMDR3
RMC2
XREP2
Data Sheet
RMC2
7
Reset Signaling Unit Counter - HDLC Channel 1
After setting this bit the SS7 signaling unit counter and error counter
are reset.The bit is cleared automatically after execution.
Note: The maximum time between writing to the CMDR2 register
Transmit Periodical Performance Report (PPR)
After setting this bit the last PPR is sent once. The bit is cleared
automatically after completion. Applies to HDLC channel 1 only.
Receive Message Complete - HDLC Channel 2
Confirmation from CPU to FALC
has been fetched following an RPF2 or RME2 interrupt, thus the
occupied space in the RFIFO2 can be released.
Transmission Repeat - HDLC Channel 2
If XREP2 is set together with XTF2 (write 24H to CMDR3), the FALC
repeatedly transmits the contents of the XFIFO2 (1 to 32 bytes)
without HDLC framing fully transparently, i.e. without flag, CRC.
The cyclic transmission is stopped with an SRES2 command or by
resetting XREP2.
H
H
and the execution of the command takes 2.5 periods of the
current system data rate. Therefore, if the CPU operates with
a very high clock rate in comparison with the FALC56's clock,
it is recommended that bit SIS.CEC should be checked before
writing to the CMDR register to avoid any loss of commands.
XREP2
389
XHF2
®
that the current frame or data block
XTF2
RSUC
XME2
T1/J1 Registers
SRES2
XPPR
FALC56 V1.2
0
PEB 2256
2002-08-27
(87)
(88)
®