PEB2256E INFINEON [Infineon Technologies AG], PEB2256E Datasheet - Page 55

• Manufacturer Part Number: PEB2256E
• Description: E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications
• Manufacturer: INFINEON [Infineon Technologies AG]

3.3.1.3
Special events in the FALC
programmable characteristics (open drain or push-pull, defined by register IPC), which
requests the CPU to read status information from the FALC
the FALC
Since only one INT request output is provided, the cause of an interrupt must be
determined by the CPU by reading the FALC
The interrupt on pin INT and the interrupt status bits are reset by reading the interrupt
status registers. Register ISR(5:0) are of type “clear on read“.
The structure of the interrupt status registers is shown in
Figure 10
Each interrupt indication of registers ISR(5:0) can be selectively masked by setting the
corresponding bit in the corresponding mask registers IMR(5:0). If the interrupt status
bits are masked they neither generate an interrupt at INT nor are they visible in ISR(5:0).
GIS, the non-maskable Global Interrupt Status Register, serves as pointer to pending
interrupts. After the FALC
should first read the Global Interrupt Status register GIS to identify the requesting
Data Sheet
Global
Interrupt
Status
Register GIS
®
.
Interrupt Interface
Interrupt Status Registers
ISR0
ISR1
ISR2
ISR3
ISR4
ISR5
®
has requested an interrupt by activating its INT pin, the CPU
®
are indicated by means of a single interrupt output with
55
ISR0
ISR2
ISR4
®
’s interrupt status registers (GIS, ISR(5:0)).
IMR0
IMR2
IMR4
Functional Description E1/T1/J1
Figure
®
, or to transfer data from/to
10.
ISR1
ISR3
ISR5
IMR1
IMR3
IMR5
FALC56 V1.2
F0127 V1.0
PEB 2256
2002-08-27