PEB2256E INFINEON [Infineon Technologies AG], PEB2256E Datasheet - Page 365

• Manufacturer Part Number: PEB2256E
• Description: E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications
• Manufacturer: INFINEON [Infineon Technologies AG]

XDOS
EQON
RLM
LL
MAS
Data Sheet
Transmit Data Out Sense
0 =
1 =
Note: If CMI coding is selected (FMR0.XC(1:0) = 01) this bit has to
Receive Equalizer On
0 =
1 =
Receive Line Monitoring
0 =
1 =
Local Loop
0
1
Master Mode
0
1
Normal operation
Slave mode
Output signals XDOP/XDON are active low. Output XOID is
active high (normal operation).
Output signals XDOP/XDON are active high. Output XOID is
active low.
-10 dB receiver: short-haul mode
-36 dB receiver: long-haul mode
Normal receiver mode
Receiver mode for receive line monitoring;
the receiver sensitivity is increased to detect resistively
attenuated signals of -20 dB (short-haul mode only)
Local loop active. The local loop-back mode disconnects the
receive lines RL1/RL2 or RDIP/RDIN from the receiver. Instead
of the signals coming from the line the data provided by system
interface is routed through the analog receiver back to the
system interface. The unipolar bit stream is transmitted
undisturbedly on the line. Receiver and transmitter coding must
be identical. Operates in analog and digital line interface mode.
In analog line interface mode data is transferred through the
complete analog receiver.
Master mode on. Setting this bit the DCO-R circuitry is
frequency synchronized to the clock (1.544, 2.048 MHz or
8 kHz, see IPC.SSYF, LIM1.DCOC) supplied by SYNC. If this
pin is connected to V
internally) the DCO-R circuitry is centered and no receive jitter
attenuation is performed (only if 1.544 or 2.048 MHz clock is
selected by resetting bit IPC.SSYF). The generated clocks are
stable.
be cleared.
The transmit frame marker XFM is independent of this bit.
365
SS
or V
DD
(or left open and pulled up to V
T1/J1 Registers
FALC56 V1.2
PEB 2256
2002-08-27
DD