PEB2256E INFINEON [Infineon Technologies AG], PEB2256E Datasheet - Page 338

• Manufacturer Part Number: PEB2256E
• Description: E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications
• Manufacturer: INFINEON [Infineon Technologies AG]

Interrupt Port Configuration (Read/Write)
Value after reset: 00
IPC
Unused bits have to be cleared.
SSYF
IC0, IC1
Common Configuration Register 1 (Read/Write)
Value after reset: 00
CCR1
BRM
EDLX
Data Sheet
7
7
Select SYNC Frequency
Only applicable in master mode (LIM0.MAS = 1) and bit CMR2.DCF
is cleared.
0
1
Interrupt Port Configuration
These bits define the function of the interrupt output stage (pin INT):
IC1
X
0
1
BOM Receive Mode - HDLC Channel 1
(significant in BOM mode only)
0
1
Enable DL-Bit Access through the Transmit FIFO - HDLC
Channel 1
A one in this bit position enables the internal DL-bit access through
the receive/transmit FIFO of the signaling controller. FMR1.EDL has
to be cleared.
BRM
H
H
Reference clock on port SYNC is 1.544/2.048 MHz
(see LIM1.DCOC)
Reference clock on port SYNC is 8 kHz
10-byte packets
Continuous reception
EDLX
IC0
0
1
1
EITS
Function
Open drain output
Push/pull output, active low
Push/pull output, active high
338
ITF
XMFA
SSYF
RFT1
IC1
T1/J1 Registers
RFT0
FALC56 V1.2
IC0
0
0
PEB 2256
2002-08-27
(09)
(08)