PEB2256E INFINEON [Infineon Technologies AG], PEB2256E Datasheet - Page 436

• Manufacturer Part Number: PEB2256E
• Description: E1/T1/J1 Framer and Line Interface Component for Long and Short Haul Applications
• Manufacturer: INFINEON [Infineon Technologies AG]

Interrupt Status Register 5 (Read)
ISR5
All bits are reset when ISR5 is read.
If bit GCR.VIS is set, interrupt statuses in ISR5 are flagged although they are masked
via register IMR5. However, these masked interrupt statuses neither generate a signal
on INT, nor are visible in register GIS.
XPR2
XPR3
RME3
RFS3
Data Sheet
XPR2
7
Transmit Pool Ready - HDLC Channel 2
A data block of up to 32 bytes can be written to the transmit FIFO2.
XPR2 enables the fastest access to XFIFO2. It has to be used for
transmission of long frames, back-to-back frames or frames with
shared flags.
Transmit Pool Ready - HDLC Channel 3
A data block of up to 32 bytes can be written to the transmit FIFO3.
XPR3 enables the fastest access to XFIFO3. It has to be used for
transmission of long frames, back-to-back frames or frames with
shared flags.
Receive Message End - HDLC Channel 3
One complete message of length less than 32 bytes, or the last part
of a frame at least 32 bytes long is stored in the receive FIFO3,
including the status byte.
The complete message length can be determined reading register
RBC3, the number of bytes currently stored in RFIFO3 is given by
RBC3(6:0). Additional information is available in register RSIS3.
Receive Frame Start - HDLC Channel 3
This is an early receiver interrupt activated after the start of a valid
frame has been detected, i.e. after an address match (in operation
modes providing address recognition), or after the opening flag
(transparent mode 0) is detected, delayed by two bytes. After an
RFS2 interrupt, the contents of
• RAL1
• RSIS3 bits 3 to 1
are valid and can be read by the CPU.
XPR3
RME3
RFS3
436
RDO3
ALLS3
XDU3
T1/J1 Registers
RPF3
FALC56 V1.2
0
PEB 2256
2002-08-27
(6D)